Source-synchronous Networks-on-chip: Circuit and Architectural Interconnect Modeling

Mandal, Ayan/ Khatri, Sunil P./ Mahapatra, Rabi

ISBN 10: 1493948172 / ISBN 13: 9781493948178

Published by Springer Verlag, 2016

About this Item

reprint edition. 156 pages. 9.25x6.10x0.38 inches. In Stock.

Seller Inventory # x-1493948172

Bibliographic Details

• Title: Source-synchronous Networks-on-chip: Circuit and Architectural Interconnect Modeling
• Publisher: Springer Verlag
• Publication Date: 2016
• Language: English
• ISBN 10: 1493948172
• ISBN 13: 9781493948178
• Binding: Paperback
• Condition: Brand New

About this title

Synopsis

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

From the Back Cover

This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.

• Describes novel methods for high-speed network-on-chip (NoC) design;
• Enables readers to understand NoC design from both circuit and architectural levels;
• Provides circuit-level details of the NoC (including clocking, router design), along with a high-speed, resonant clocking style which is used in the NoC;
• Includes architectural simulations of the NoC, demonstrating significantly superior performance over the state-of-the-art.