Globalization of the integrated circuit (IC) supply chains led to many potential vulnerabilities. Several attack scenarios can exploit these vulnerabilities to reverse engineer IC designs or to insert malicious trojan circuits.
Split manufacturing refers to the process of splitting an IC design into multiple parts and fabricating these parts at two or more foundries such that the design is secure even when some or all of those foundries are potentially untrusted. Realizing its security benefits, researchers have proposed split fabrication methods for 2D, 2.5D, and the emerging 3D ICs. Both attack methods against split designs and defense techniques to thwart those attacks while minimizing overheads have steadily progressed over the past decade.
This book presents a comprehensive review of the state-of-the-art and emerging directions in design splitting for secure split fabrication, design recognition and recovery attacks against split designs, and design techniquesto defend against those attacks. Readers will learn methodologies for secure and trusted IC design and fabrication using split design methods to protect against supply chain vulnerabilities.
Ranga Vemuri has been on the faculty of the Electrical Engineering and Computer Science Department at the University of Cincinnati since 1989 and is currently a Professor. He directs the Digital Design Environments Lab. His interests span various topics within Hardware Trust, Correctness and Security; VLSI Design and Architectures; Formal Methods and Formal Verification; Electronic Design Automation; Reconfigurable Computing and FPGAs. He and his students have published over 300 papers and have received several Best Paper Awards and nominations. Prof. Vemuri graduated 42 PhD and 90 MS students. His research has been funded by AFRL, DAGSI, DARPA, NSF, State of Ohio and various industries including EDAptive Computing Inc. Prof. Vemuri was an Associate Editor of the IEEE Transactions on VLSI and a Guest Editor of the IEEE Computer.
Suyuan Chen received a Ph.D. degree in Electrical Engineering from the University of Cincinnati in 2019. Currently, he is an ASIC Engineer at Apple Inc. where his work deals with SoC design using state-of-the-art 7nm, 5nm and 3nm CMOS technologies. His interests span a variety of topics in Hardware Security, LSI/AMS IC Design Methodologies, and Computer Aided Design.
