Static Timing Analysis for Nanometer Designs : A Practical Approach
J. Bhasker
Sold by AHA-BUCH GmbH, Einbeck, Germany
AbeBooks Seller since August 14, 2006
New - Hardcover
Condition: New
Quantity: 2 available
Add to basketSold by AHA-BUCH GmbH, Einbeck, Germany
AbeBooks Seller since August 14, 2006
Condition: New
Quantity: 2 available
Add to basketNeuware - iming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques.
Seller Inventory # 9780387938196
Static Timing Analysis for Nanometer Designs: A Practical Approach is a reference for both beginners as well as professionals working in the area of static timing analysis for semiconductors. This book provides a blend of underlying theoretical background and in-depth coverage of timing verification using static timing analysis. The relevant topics such as cell and interconnect modeling, timing calculation, and crosstalk, which can impact the timing of a nanometer design are covered in detail. Timing checks at various process, environment, and interconnect corners, including on-chip variations, are explained in detail. Verification of hierarchal building blocks, full chip, including timing verification of special IO interfaces are covered in detail. Appendices provide complete coverage of SDC, SDF, and SPEF formats.
This book is written for professionals working in the area of chip design, timing verification of ASICs and also for graduate students specializing in logic and chip design. Professionals who are beginning to use static timing analysis or are already well-versed in static timing analysis will find this book useful.
Static Timing Analysis for Nanometer Designs serves as a reference for a graduate course in chip design and as a text for a course in timing verification for working engineers.
"About this title" may belong to another edition of this title.
General Terms and Conditions and Customer Information / Privacy Policy
I. General Terms and Conditions
§ 1 Basic provisions
(1) The following terms and conditions apply to all contracts that you conclude with us as a provider (AHA-BUCH GmbH) via the Internet platforms AbeBooks and/or ZVAB. Unless otherwise agreed, the inclusion of any of your own terms and conditions used by you will be objected to
(2) A consumer within the meaning of the following regulations is any natural person who concludes...
More InformationWe ship your order after we received them
for articles on hand latest 24 hours,
for articles with overnight supply latest 48 hours.
In case we need to order an article from our supplier our dispatch time depends on the reception date of the articles, but the articles will be shipped on the same day.
Our goal is to send the ordered articles in the fastest, but also most efficient and secure way to our customers.