As a result of aggressive downscaling, short-channel effects (SCEs) become a major threat for future downscaling especially in the sub-100nm region. In order to extend the International Technology Road-map for Semiconductors (ITRS) road-map beyond 100nm, Double-Gate (DG) MOSFET evinces himself as a major promising candidate due to its higher scaling capability. In this book, modelling using a pseudo- two-dimensional (2D) analysis was presented to explore the effect of scaling especially for subthreshold characteristics of short-channel DG and conventional single gate MOSFET.

About the Author

Dr. Angsuman Sarkar is presently serving as an Assistant Professor of Electronics and Communication Engineering in Kalyani Government Engineering College, West Bengal, India. He received the M.Tech degree in VLSI & Microelectronics from Jadavpur University and later he was awarded the Ph.D degree from Jadavpur University.

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