Symbolic Model Checking

Kenneth L McMillan

ISBN 10: 0792393805 / ISBN 13: 9780792393801

Published by Springer Jul 1993, 1993

About this Item

Neuware - Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware. The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention.

Seller Inventory # 9780792393801

Bibliographic Details

• Title: Symbolic Model Checking
• Publisher: Springer Jul 1993
• Publication Date: 1993
• Language: English
• ISBN 10: 0792393805
• ISBN 13: 9780792393801
• Binding: Buch
• Condition: Neu
• Dimensions: 241W x 160H x 18D millimeters 241 millimeters width by 160 millimeters height by 18 millimeters depth
• Weight: 494 grams

About this title

Synopsis

Formal verification means having a mathematical model of a system, a language for specifying desired properties of the system in a concise, comprehensible and unambiguous way, and a method of proof to verify that the specified properties are satisfied. When the method of proof is carried out substantially by machine, we speak of automatic verification. Symbolic Model Checking deals with methods of automatic verification as applied to computer hardware.
The practical motivation for study in this area is the high and increasing cost of correcting design errors in VLSI technologies. There is a growing demand for design methodologies that can yield correct designs on the first fabrication run. Moreover, design errors that are discovered before fabrication can also be quite costly, in terms of engineering effort required to correct the error, and the resulting impact on development schedules. Aside from pure cost considerations, there is also a need on the theoretical side to provide a sound mathematical basis for the design of computer systems, especially in areas that have received little theoretical attention.