Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs

Balsha R. Stanisic, L. Richard Carley, Rob A. Rutenbar

ISBN 10: 0792397347 / ISBN 13: 9780792397342

Published by Springer US, 1996

About this Item

Zustand: Gut | Sprache: Englisch | Produktart: Bücher | In the early days of VLSI, the design of the power distribution for an integrated cir­ cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi­ vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over­ lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num­ bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec­ tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.

Seller Inventory # 3033440/3

Bibliographic Details

• Title: Synthesis of Power Distribution to Manage Signal Integrity in Mixed-Signal ICs
• Publisher: Springer US
• Publication Date: 1996
• Language: English
• ISBN 10: 0792397347
• ISBN 13: 9780792397342
• Binding: Hardcover
• Condition: Gut
• Seller catalogs:
  • Bücher

About this title

Synopsis

In the early days of VLSI, the design of the power distribution for an integrated cir­ cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi­ vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over­ lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num­ bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec­ tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.