SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications

Ashok B. Mehta

ISBN 10: 1461473233 / ISBN 13: 9781461473237

Published by Springer New York, Springer New York, 2013

About this Item

Druck auf Anfrage Neuware - Printed after ordering - This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage. Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question 'have we functionally verified everything'. Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects. Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

Seller Inventory # 9781461473237

Bibliographic Details

• Title: SystemVerilog Assertions and Functional Coverage : Guide to Language, Methodology and Applications
• Publisher: Springer New York, Springer New York
• Publication Date: 2013
• Language: English
• ISBN 10: 1461473233
• ISBN 13: 9781461473237
• Binding: Buch
• Condition: Neu
• Dimensions: 241W x 160H x 26D millimeters 241 millimeters width by 160 millimeters height by 26 millimeters depth
• Weight: 752 grams

About this title

Synopsis

This book provides a hands-on, application-oriented guide to the language and methodology of both SystemVerilog Assertions and SytemVerilog Functional Coverage.  Readers will benefit from the step-by-step approach to functional hardware verification, which will enable them to uncover hidden and hard to find bugs, point directly to the source of the bug, provide for a clean and easy way to model complex timing checks and objectively answer the question ‘have we functionally verified everything’.  Written by a professional end-user of both SystemVerilog Assertions and SystemVerilog Functional Coverage, this book explains each concept with easy to understand examples, simulation logs and applications derived from real projects.  Readers will be empowered to tackle the modeling of complex checkers for functional verification, thereby drastically reducing their time to design and debug.

About the Author

Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.