SystemVerilog for Hardware Description
Taraate
Sold by Lucky's Textbooks, Dallas, TX, U.S.A.
AbeBooks Seller since July 22, 2022
New - Hardcover
Condition: New
Quantity: Over 20 available
Add to basketSold by Lucky's Textbooks, Dallas, TX, U.S.A.
AbeBooks Seller since July 22, 2022
Condition: New
Quantity: Over 20 available
Add to basketVaibbhav Taraate is an entrepreneur and mentor at "Semiconductor Training @ Rs. 1". He holds a B.E. (Electronics) degree from Shivaji University, Kolhapur in 1995. He completed his M.Tech. (Aerospace Control and Guidance) in 1999 from IIT Bombay. He has over 18 years of experience in semi-custom ASIC and FPGA design, primarily using HDL languages such as Verilog and VHDL. He has worked with few multinational corporations as a consultant, senior design engineer, and technical manager. His areas of expertise include RTL design using VHDL, RTL design using Verilog, complex FPGA-based design, low power design, synthesis/optimization, static timing analysis, system design using microprocessors, high speed VLSI designs, and architecture design of complex SOCs.
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