TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method

Muddapu Parvathi (u. a.)

ISBN 10: 6202095466 / ISBN 13: 9786202095464

Published by LAP LAMBERT Academic Publishing, 2017

About this Item

TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method | Muddapu Parvathi (u. a.) | Taschenbuch | 252 S. | Englisch | 2017 | LAP LAMBERT Academic Publishing | EAN 9786202095464 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 110685090

Bibliographic Details

• Title: TESTING OF eSRAM USING MMC- Algorithm And Parasitic Extraction Method
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2017
• Language: English
• ISBN 10: 6202095466
• ISBN 13: 9786202095464
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 16D millimeters 220 millimeters width by 150 millimeters height by 16 millimeters depth
• Weight: 393 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

The intention of the book is to highlight core issues of current technology relevant to embedded SRAM, testing methods and need of new test requirements. The importance of March algorithms and in depth working including examples were clearly shown. The failures of existing March algorithms and hence the development of MMC- (Modified March C-) algorithm will increase the reader interest in exploring much more test algorithms required for e-SRAM. Above this, the testing method using Parasitic extraction of R & C developed using Cadence tools and Microwind is highlight of the investigations. The layout level parasitic extraction of R&C method was applied on all possible SRAM fault models using 'bridge/short' created in electrical circuit environment. Using parasitic memory effect, fault detection dictionary was an outcome this research in which each fault model behavior is highlighted in terms of R & C at different technology nodes. The chosen technology nodes are 90nm, 120nm, and 180nm. This method was extended to few two cell fault models and discussed on coupling faults.

About the Author

Dr. M. Parvathi,having 17 years of teaching experience, presently working as Professor in BVRITH College of Engineering for Women, have done her B.tech (ECE) from NIT Warangal, and M. Tech from JNTU Hyderabad. She obtained her Ph.D degree in the area of VLSI design from JNTUK Kakinada, AP, India. She guided over 15 PG scholars and 40 UG projects.