Transactions on High-Performance Embedded Architectures and Compilers II (Lecture Notes in Computer Science, 5470)
ISBN 10: 3642009034 ISBN 13: 9783642009037
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caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.
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Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.
This second issue contains 15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections. The first section contains extended versions of the top five papers from the 2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of ten papers covering topics such as microarchitecture, memory systems, code generation, and performance modeling.
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Title: Transactions on High-Performance Embedded ...
Publisher: Springer
Publication Date: 2009
Binding: Soft cover
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Transactions on High-Performance Embedded Architectures and Compilers II
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Taschenbuch. Condition: Neu. Transactions on High-Performance Embedded Architectures and Compilers II | Per Stenström (u. a.) | Taschenbuch | xiv | Englisch | 2009 | Springer | EAN 9783642009037 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu. Seller Inventory # 101626133
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Transactions on High-Performance Embedded Architectures and Compilers II
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ISBN 10: 3642009034
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation . Seller Inventory # 5043233
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Transactions on High-Performance Embedded Architectures and Compilers II
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.Thissecond issue contains15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections.The first section contains extended versions ofthetop five papersfrom the2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of tenpapers covering topics such as microarchitecture, memory systems, code generation, and performance modeling. 327 pp. Englisch. Seller Inventory # 9783642009037
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Transactions on High-Performance Embedded Architectures and Compilers II (Lecture Notes in Computer Science)
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Transactions on High-Performance Embedded Architectures and Compilers II
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Transactions on HiPEAC aims at the timely dissemination of research contributions in computer architecture and compilation methods for high-performance embedded computer systems. Recognizing the convergence of embedded and general-purpose computer systems, this journal publishes original research on systems targeted at specific computing tasks as well as systems with broad application bases. The scope of the journal therefore covers all aspects of computer architecture, code generation and compiler optimization methods of interest to researchers and practitioners designing future embedded systems.Thissecond issue contains15 papers carefully reviewed and selected out of 31 submissions and is divided into two sections.The first section contains extended versions ofthetop five papersfrom the2nd International Conference on High-Performance Embedded Architectures and Compilers (HiPEAC 2007) held in Ghent, Belgium, in January 2007. The second section consists of tenpapers covering topics such as microarchitecture, memory systems, code generation, and performance modeling. Seller Inventory # 9783642009037
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