A VHDL Synthesis Primer, Second Edition (Paperback)
J. Bhasker
Sold by AussieBookSeller, Truganina, VIC, Australia
AbeBooks Seller since June 22, 2007
New - Soft cover
Condition: New
Quantity: 1 available
Add to basketSold by AussieBookSeller, Truganina, VIC, Australia
AbeBooks Seller since June 22, 2007
Condition: New
Quantity: 1 available
Add to basketPaperback. Learn to model for synthesis using VHDL. See the details of how VHDL gets translated into logic gates in this book. Also, see how hardware elements are described in synthesizable VHDL. This book is a must primer for anyone who is beginning to learn synthesis using VHDL. A chapter on verification explains the many causes of simulation mismatches between pre and post synthesis models and how to avoid these. Modeling guidelines are also provided to help improve synthesis results. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability.
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