VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design

Golze, Ulrich; Blinzer, P. [Assistant]; Cochlovius, E. [Assistant]; Schäfers, M. [Assistant]; Wachsmann, K.-P. [Assistant];

ISBN 10: 3540600329 / ISBN 13: 9783540600329

Published by Springer, 1996

About this Item

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Bibliographic Details

• Title: VLSI Chip Design with the Hardware Description Language VERILOG: An Introduction Based on a Large RISC Processor Design
• Publisher: Springer
• Publication Date: 1996
• Language: English
• ISBN 10: 3540600329
• ISBN 13: 9783540600329
• Binding: Hardcover
• Condition: New
• Weight: 25 ounces

About this title

Synopsis

The art of transforming a circuit idea into a chip has changed permanently. Formerly, the electrical, physical and geometrical tasks were predominant. Later, mainly net lists of gates had to be constructed. Nowadays, hardware description languages (HDL) similar to programming languages are central to digital circuit design. HDL-based design is the main subject of this book.
After emphasizing the economic importance of chip design as a key technology, the book deals with VLSI design (Very Large Scale Integration), the design of modern RISC processors, the hardware description language VERILOG, and typical modeling techniques. Numerous examples as well as a VERILOG training simulator are included on a disk.

From the Back Cover

This book introduces to modern design of large chips. A powerful RISC processor in the range of a SPARC is apecified in a hardware description language (HDL), it is developed hierarchically and is finally sent as a gate model to the silicon vendor LSI Logic for production. The resulting processor on a semi-custom gate-array chip with more than 50.000 used gates and an efficiency of up to 40 MIPS is tested on an automatic test equipment and a testboard. The book also introduces thoroughly to the HDL VERILOG. The included disk contains more than 40 small and medium sized executable VERILOG examples, the large processor models and the VERILOG simulator VeriWell running on PC or SPARC.