VLSI Design for Video Coding

Lin Youn-Long Steve Kao Chao-Yang Kuo Hung-Chih

ISBN 10: 1441909583 / ISBN 13: 9781441909589

Published by Springer, 2010

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PRINT ON DEMAND pp. 190.

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Bibliographic Details

• Title: VLSI Design for Video Coding
• Publisher: Springer
• Publication Date: 2010
• Language: English
• ISBN 10: 1441909583
• ISBN 13: 9781441909589
• Binding: Hardcover
• Condition: New

About this title

Synopsis

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book will present VLSI architectural design and chip implementation for high definition H.264/AVC video encoding, using a state-of-the-art video application, with complete VLSI prototype, via FPGA/ASIC. It will serve as an invaluable reference for anyone interested in VLSI design and high-level (EDA) synthesis for video.

From the Back Cover

Back Cover Copy

VLSI Design for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

High definition video requires substantial compression in order to be transmitted or stored economically. Advances in video coding standards from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have provided ever increasing coding efficiency, at the expense of great computational complexity which can only be delivered through massively parallel processing.

This book presents VLSI architectural design and chip implementation for high definition H.264/AVC video encoding with a complete FPGA prototype. It serves as an invaluable reference for anyone interested in VLSI design for video coding.

• Presents state-of-the-art VLSI architectural design and chip implementation for high definition H.264/AVC video encoding;

• Employs massively parallel processing to deliver 1080pHD, with efficient design that can be prototyped via FPGA;

• Every subsystem is presented from standard specification, algorithmic description, design considerations, timing planning, block diagram to test-bench verification;