Variability Tolerant Networks on Chip

Language: English

Published by LAP LAMBERT Academic Publishing Apr 2015, 2015

3659660906 / 9783659660900

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -NoC have been successfully replacing interconnects in multi-core chip. As technology scales down, process variations cause NoC links designed to be identical to have different electrical properties. We propose statistical design methodology that uses a statistical guard to tolerate variations with lower guard than conventional worst-case design. Thus saving power at low failure rate. A variability-aware NoC topology and geometry scaling, in addition to topology evaluation from variation perspective help the designer to perform scaling and choose the topology with lower variations for different technology nodes and NoC size. Finally, variability-aware routing algorithms make use of process variability link failure probability and adapt routing to reduce the NoC failure rate. 132 pp. Englisch.

Seller Inventory # 9783659660900

Title
Variability Tolerant Networks on Chip
Author
Eman Gawish
Publisher
LAP LAMBERT Academic Publishing Apr 2015
Publication year
2015
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3659660906
ISBN 13
9783659660900
Item weight
215 grams
Dimensions
220x150x8 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

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BuchWeltWeit Ludwig Meier e.K.

Germany