Verification and Synthesis of Digital Circuits : High-level Synthesis and Equivalence Checking

Language: English

Published by LAP LAMBERT Academic Publishing, 2010

3838398130 / 9783838398136

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Seller: AHA-BUCH GmbH, Einbeck, GermanyAHA-BUCH GmbH

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nach der Bestellung gedruckt Neuware - Printed after ordering - Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the special characteristics of each synthesis sub-task separately. This book is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with data-paths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A high-level synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support hand-in-hand synthesis and verification.

Seller Inventory # 9783838398136

Title
Verification and Synthesis of Digital Circuits : High-level Synthesis and Equivalence Checking
Author
Chandan Karfa
Publisher
LAP LAMBERT Academic Publishing
Publication year
2010
Condition
Neu
Binding
Taschenbuch
Language
English
ISBN 10
3838398130
ISBN 13
9783838398136
Item weight
322 grams
Dimensions
220x150x13 mm

AHA-BUCH GmbH

Einbeck, Germany

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AbeBooks seller since August 14, 2006

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