Verification and Synthesis of Digital Circuits | High-level Synthesis and Equivalence Checking

Chandan Karfa (u. a.)

ISBN 10: 3838398130 / ISBN 13: 9783838398136

Published by LAP LAMBERT Academic Publishing, 2010

About this Item

Verification and Synthesis of Digital Circuits | High-level Synthesis and Equivalence Checking | Chandan Karfa (u. a.) | Taschenbuch | 204 S. | Englisch | 2010 | LAP LAMBERT Academic Publishing | EAN 9783838398136 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 107341512

Bibliographic Details

• Title: Verification and Synthesis of Digital Circuits | High-level Synthesis and Equivalence Checking
• Publisher: LAP LAMBERT Academic Publishing
• Publication Date: 2010
• Language: English
• ISBN 10: 3838398130
• ISBN 13: 9783838398136
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 13D millimeters 220 millimeters width by 150 millimeters height by 13 millimeters depth
• Weight: 322 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

Advances in VLSI technology have enabled its deployment into complex circuits. Synthesis flow of such circuits comprises various phases where each phase performs the task algorithmically providing for ingenious interventions of experts. The gap between the original behaviour and the finally synthesized circuit is too wide to be analyzed by any reasoning mechanism. The validation tasks, therefore, must be planned to go hand-in-hand with each phase of synthesis with scope to handle the special characteristics of each synthesis sub-task separately. This book is concerned with hand-in-hand verification and (high-level) synthesis of digital circuits. The verification problem is formulated as equivalence checking between two finite state machines with data-paths (FSMD). The difficulties of each phase are identified and the verification methods based on equivalence of two FSMDs have been formulated accordingly. A high-level synthesis tool, called structured architecture synthesis tool (SAST), has been developed which support hand-in-hand synthesis and verification.

About the Author

All authors are with the Department of Computer Science and Engineering, IIT Kharagpur. Chandan Karfa (pictured) is a senior PhD student supported by a Microsoft Research India PhD Fellowship. Dipankar Sarkar and Chittaranjan Mandal are faculty members. The authors are active in CAD for synthesis and verification of digital circuits and systems.