Verification Techniques for System-Level Design

Language: English

Published by Elsevier Science Nov 2007, 2007

0123706165 / 9780123706164

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Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, GermanyBuchWeltWeit Ludwig Meier e.K.

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This item is printed on demand - it takes 3-4 days longer - Neuware -This book will explain how to verify SoC (Systems on Chip) logic designs using 'formal? and 'semiformal? verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in 'functional? verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been gaining popularity.For higher design productivity, it is essential to debug designs as early as possible, which this book facilitates. This book covers all aspects of high-level formal and semiformal verification techniques for system level designs. 256 pp. Englisch.

Seller Inventory # 9780123706164

Title
Verification Techniques for System-Level Design
Author
Mukul Prasad
Publisher
Elsevier Science Nov 2007
Publication year
2007
Condition
Neu
Binding
Buch
Language
English
ISBN 10
0123706165
ISBN 13
9780123706164
Item weight
667 grams
Dimensions
235x194x22 mm

BuchWeltWeit Ludwig Meier e.K.

Bergisch Gladbach, Germany

5-star seller

AbeBooks seller since January 11, 2012

Shipping rates from Germany to U.S.A.

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BuchWeltWeit Ludwig Meier e.K.

Germany