Verification of Temporal Properties in Embedded Software | based on Assertion and Semiformal Verification Approaches

Djones Lettnin

ISBN 10: 3838112075 / ISBN 13: 9783838112077

Published by Südwestdeutscher Verlag für Hochschulschriften, 2009

About this Item

Verification of Temporal Properties in Embedded Software | based on Assertion and Semiformal Verification Approaches | Djones Lettnin | Taschenbuch | 160 S. | Englisch | 2009 | Südwestdeutscher Verlag für Hochschulschriften | EAN 9783838112077 | Verantwortliche Person für die EU: BoD - Books on Demand, In de Tarpen 42, 22848 Norderstedt, info[at]bod[dot]de | Anbieter: preigu.

Seller Inventory # 101424787

Bibliographic Details

• Title: Verification of Temporal Properties in Embedded Software | based on Assertion and Semiformal Verification Approaches
• Publisher: Südwestdeutscher Verlag für Hochschulschriften
• Publication Date: 2009
• Language: English
• ISBN 10: 3838112075
• ISBN 13: 9783838112077
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 220W x 150H x 11D millimeters 220 millimeters width by 150 millimeters height by 11 millimeters depth
• Weight: 256 grams
• Seller catalogs:
  • Bücher

About this title

Synopsis

For some years ago the main statement among verification engineers was "Bugs in hardware cost money". Nowadays, the embedded software is playing an important role in the embedded systems industry and the statement can be updated to "Bugs in hardware and in software cost a lot of money". Embedded software is very powerful in embedded systems in order to implement important functionalities and functional innovations. The developing costs of embedded software are becoming huge and its amount in safety critical systems is increasing. Therefore, the verification of complex systems needs to consider the verification of both hardware and embedded software modules. The most commonly used approaches to verify embedded software are based on co- simulation or on co-debugging, which consume long verification time and additionally have coverage limitations. Formal verification assures complete coverage, but is limited to the size of the module that can be verified. This dissertation extends the conventional verification limitations with methodologies that are based on temporal properties and formal verification.

About the Author

Djones Lettnin has Master's in Electric Engineering at Catholic University of Rio Grande do Sul (2004), Brazil, and PhD. in Computer Engineering at the Eberhard Karls University of Tübingen (2009), Germany. He has interest in design and veri?cation of embedded systems.