The Verilog® Hardware Description Language

Donald E. Thomas|Philip R. Moorby

ISBN 10: 1461367840 / ISBN 13: 9781461367840

Published by Springer US, 2012

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Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and. Seller Inventory # 4194947

Bibliographic Details

Title: The Verilog® Hardware Description Language

Publisher: Springer US

Publication Date: 2012

Binding: Soft cover

Condition: New

About this title

Synopsis:

The Verilog language is a hardware description language which provides a means of specifying a digital system at a wide range of levels of abstraction. The language supports the early conceptual stages of design with its behavioral level of abstraction, and the later implementation stages with its structural level of abstraction. The language provides hierarchical constructs, allowing the designer to control the complexity of a description. Verilog was originally designed in the winter of 1983/84 as a proprietary verification/simulation product. Since then, several other proprietary analysis tools have been developed around the language, including a fault simulator and a timing analyzer; the language being instrumental in providing consistency across these tools. Now, the language is openly available for any tool to read and write. This book introduces the language. It is sometimes difficult to separate the language from the simulator tool because the dynamic aspects of the language are defined by the way the simulator works. Where possible, we have stayed away from simulator-specific details and concentrated on design specification, but have included enough information to be able to have working executable models. The book takes a tutorial approach to presenting the language.