Verilog Hdl Synthesis: A Practical Primer

J. Bhasker

ISBN 10: 0965039153 / ISBN 13: 9780965039154

Published by Star Galaxy Pub, 1998

Pages can have notes/highlighting. Spine may show signs of wear. ~ ThriftBooks: Read More, Spend Less 0.88. Seller Inventory # G0965039153I3N00

Synopsis:

With this book, you can:

- Start writing synthesizable Verilog models quickly.

- See what constructs are supported for synthesis and how these map to hardware so that you can get the desired logic.

- Learn techniques to help avoid having functional mismatches.

- Immediately start using many of the models for commonly used hardware elements described for your own use or modify these for your own application.

About the Author: J. Bhasker is the chair of the IEEE PAR 1364.1 Verilog Synthesis Interoperability Working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the Archsyn synthesis system developed at Bell Labs. He has taught Verilog HDL and Verilog HDL synthesis to many AT&T / Lucent designers. He is also the author of the bestselling book "A Verilog HDL Primer"'.

Bibliographic Details

Title: Verilog Hdl Synthesis: A Practical Primer
Publisher: Star Galaxy Pub
Publication Date: 1998
Binding: Paperback
Condition: Good
Dust Jacket Condition: No Jacket