Wafer-Level Integrated Systems : Implementation Issues

Stuart K. Tewksbury

ISBN 10: 1461288983 / ISBN 13: 9781461288985

Published by Springer US, Springer US, 2012

About this Item

Druck auf Anfrage Neuware - Printed after ordering - From the perspective of complex systems, conventional Ie's can be regarded as 'discrete' devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term 'wafer level' is perhaps more appropriate than 'wafer-scale'. A 'wafer-level' monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, 'wafer-scale' merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.

Seller Inventory # 9781461288985

Bibliographic Details

• Title: Wafer-Level Integrated Systems : Implementation Issues
• Publisher: Springer US, Springer US
• Publication Date: 2012
• Language: English
• ISBN 10: 1461288983
• ISBN 13: 9781461288985
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 26D millimeters 235 millimeters width by 155 millimeters height by 26 millimeters depth
• Weight: 715 grams

About this title

Synopsis

From the perspective of complex systems, conventional Ie's can be regarded as "discrete" devices interconnected according to system design objectives imposed at the circuit board level and higher levels in the system implementation hierarchy. However, silicon monolithic circuits have progressed to such complex functions that a transition from a philosophy of integrated circuits (Ie's) to one of integrated sys­ tems is necessary. Wafer-scale integration has played an important role over the past few years in highlighting the system level issues which will most significantly impact the implementation of complex monolithic systems and system components. Rather than being a revolutionary approach, wafer-scale integration will evolve naturally from VLSI as defect avoidance, fault tolerance and testing are introduced into VLSI circuits. Successful introduction of defect avoidance, for example, relaxes limits imposed by yield and cost on Ie dimensions, allowing the monolithic circuit's area to be chosen according to the natural partitioning of a system into individual functions rather than imposing area limits due to defect densities. The term "wafer­ level" is perhaps more appropriate than "wafer-scale". A "wafer-level" monolithic system component may have dimensions ranging from conventional yield-limited Ie dimensions to full wafer dimensions. In this sense, "wafer-scale" merely represents the obvious upper practical limit imposed by wafer sizes on the area of monolithic circuits. The transition to monolithic, wafer-level integrated systems will require a mapping of the full range of system design issues onto the design of monolithic circuit.