Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC | XILINX HDLC and CRC Checking

Neeraj Mishra

ISBN 10: 3659341185 / ISBN 13: 9783659341182

Published by LAP Lambert Academic Publishing, 2013

About this Item

Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC | XILINX HDLC and CRC Checking | Neeraj Mishra | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783659341182 | Verantwortliche Person für die EU: LAP Lambert Academic Publishing, Brivibas Gatve 197, 1039 RIGA, LETTLAND, customerservice[at]vdm-vsg[dot]de | Anbieter: preigu.

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Bibliographic Details

• Title: Xilinx HDLC Supporting IP over SONET And Checking 16,32Bit CRC | XILINX HDLC and CRC Checking
• Publisher: LAP Lambert Academic Publishing
• Publication Date: 2013
• Language: English
• ISBN 10: 3659341185
• ISBN 13: 9783659341182
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 7W x 150H x 220D millimeters 7 millimeters width by 150 millimeters height by 220 millimeters depth
• Weight: 166 grams
• Seller catalogs:
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About this title

Synopsis

In the present work of Xilinx HDLC controller. HDLC operates at the data link layer of the OSI Model main focus of the is to understand the data link layer and develop a protocol which can offer its services to the layer above it i.e. is the network layer and the layer below it i.e. the physical layer. The function of this protocol controller is to perform a number of separate activities like physical addressing, to check for errors, flow control design of HDLC Controller and simulation design and implement a high performance. This will then be coded in a hardware description language (VHDL). The functioning of the coded design is to be simulated on simulation software (e.g. Model Sim.).After proper simulation, the design is to be synthesized and then translated to a structural architecture in terms of the components on the target FPGA device (Spartan 3) and the perform the post-translate simulation in order to ensure the proper functioning of the design after translation. After the successful simulation of the post-translate model the design is mapped to the existing slices of the FPGA and the post-map model simulated.The objective is to run the programmed FPGA high as possible.

About the Author

Er. Neeraj Kumar Mishra received his M.Tech degree (HONs EC) from Amity University, India in 2012.His areas of interest are VHDL, DSP, Wireless Communication, Signal Processing & Application etc.And Twelve research Paper Published in various conferences.