Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford

Moore, Will; Maly, Wojciech

ISBN 10: 085274398X / ISBN 13: 9780852743980

Published by CRC Press, 1988

About this Item

A copy that has been read, remains in good condition. All pages are intact, and the cover is intact. The spine and cover show signs of wear. Pages can include notes and highlighting and show signs of wear, and the copy can include "From the library of" labels or previous owner inscriptions. 100% GUARANTEE! Shipped with delivery confirmation, if you're not satisfied with purchase please return item! Ships via media mail.

Seller Inventory # OTV.085274398X.G

Bibliographic Details

• Title: Yield Modelling and Defect Tolerance in VLSI, Papers Presented at the INT Workshop on Designing for Yield, 1-3 July 1987, Oxford
• Publisher: CRC Press
• Publication Date: 1988
• Language: English
• ISBN 10: 085274398X
• ISBN 13: 9780852743980
• Binding: Hardcover
• Condition: good

About this title

Synopsis

Papers of the International Workshop on Designing for Yield, Oxford, July 1987. Objectives include discussion of topics in VLSI and designing integrated circuits to yield targets. On yield loss mechanisms and defect tolerance, alternative prospects, catastrophic yield loss models, parametric yield l