Robin Garg

Robin is a Design Verification Architect and specializes in Functional Verification, Power Aware Design Verification, UPF Design, and DV Left Shift Methodologies. He has extensive hands-on experience working with teams and stakeholders across the globe. He has successfully lead (first pass Silicon) end-to-end product verification lifecycle at Subsystems and SoC levels for multiple generations of Server, Client Graphics, Mobile, and IoT products.

Robin is a well known face in the semiconductor industry. He is a published Author (bestseller book), and Instructor of multiple courses (among Top 3% worldwide). He is Technical Program Committee member for DVCON India and has multiple Technical Paper and Poster Presentations spanning across DV, with his most recent presentation being on “Low Power DV Sign-off of Complex SoCs” in CDNLive Bangalore 2022.