Anuj Gupta

Anuj Gupta is a mask layout and custom memory design leader with over two decades of experience in advanced-node semiconductor technologies, SRAM architectures, and physical layout optimization. He currently serves as an ICT5 Layout and Mask Design Engineer at Apple, focusing on power circuits, advanced technology enablement, and design-technology co-optimization (DTCO) across cutting-edge process nodes down to 2nm.

Earlier in his career, Anuj held key technical and leadership roles at GlobalFoundries and ARM, spearheading the development of advanced SRAM test structures, emerging memory bitcells (ReRAM/MRAM), and large-scale memory compiler platforms. Over his career, he has successfully contributed to more than 50 production tape-outs, holds several granted U.S. patents in memory cell and wordline architectures, and integrates AI-assisted methodologies into modern layout analysis.

Anuj earned his Master of Science with Distinction in VLSI System Design (Silver Medalist) from Coventry University, UK, and his AMIETE in Electronics and Communication Engineering from IETE, India, where he has been an Associate Member since 2007. He is the author of two academic books on SRAM architectures and low-jitter PLL modeling published by LAP Lambert Academic Publishing.