Andreas Burg (103 results)

Condition: New. pp. 235.

Condition: New. pp. 248.

Paperback. Condition: Brand New. rep rev edition. 248 pages. 9.25x6.10x0.59 inches. In Stock.

Hardcover. Condition: Gut. 33,5x25cm; 292 S. Hardcover. überw. Ill. Zustand: Sehr Gut, ungelesen (Innen); Einband (Außen) hat geringe Gebrauchsspuren; Seitlicher Schnitt ist in der Mitte geringfügig angestaubt; * Die Photos sind original von uns erstellt worden, u.a. erkennbar an einem kleinen weißen Stück Papier im oberen Schnitt. Ab und an verwenden Suchmaschinen Verlagsphotos, bei den Portalen selbst, werden aber nur unsere Originalphotos gezeigt.…

Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.…

Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book contains extended and revised versions of the best papers presented at the 20th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2012, held in Santa Cruz, CA, USA, in October 2012. The 12 papers included in the book were carefully reviewed and selected from the 33 full papers presented at the conference. The papers cover a wide range of topics in VLSI technology and advanced research. They address the current trend toward increasing chip integration and technology process advancements bringing about stimulating new challenges both at the physical and system-design levels, as well as in the test of these systems.…

Condition: New.

Condition: As New. Unread book in perfect condition.

Condition: New.

Condition: New.

Condition: New.

Condition: New.

Condition: As New. Unread book in perfect condition.

Condition: New. In English.

Hardback. Condition: New. 1st ed. 2018. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.…

Condition: New. In English.

Condition: New.

Condition: New.

Condition: New.

Condition: As New. Unread book in perfect condition.

Hardcover. Condition: Brand New. 146 pages. 9.25x6.25x0.50 inches. In Stock.

Condition: As New. Unread book in perfect condition.

Condition: New. In German.

Paperback. Condition: Brand New. reprint edition. 146 pages. 9.25x6.10x0.36 inches. In Stock.

Condition: New. pp. 146.

Hardback. Condition: New. 1st ed. 2018. This book pioneers the field of gain-cell embedded DRAM (GC-eDRAM) design for low-power VLSI systems-on-chip (SoCs). Novel GC-eDRAMs are specifically designed and optimized for a range of low-power VLSI SoCs, ranging from ultra-low power to power-aware high-performance applications. After a detailed review of prior-art GC-eDRAMs, an analytical retention time distribution model is introduced and validated by silicon measurements, which is key for low-power GC-eDRAM design. The book then investigates supply voltage scaling and near-threshold voltage (NTV) operation of a conventional gain cell (GC), before presenting novel GC circuit and assist techniques for NTV operation, including a 3-transistor full transmission-gate write port, reverse body biasing (RBB), and a replica technique for optimum refresh timing. Next, conventional GC bitcells are evaluated under aggressive technology and voltage scaling (down to the subthreshold domain), before novel bitcells for aggressively scaled CMOS nodes and soft-error tolerance as presented, including a 4-transistor GC with partial internal feedback and a 4-transistor GC with built-in redundancy.…

Condition: New.

Softcover/Paperback. 7., überarb. und erw. Aufl. XVIII, 604 S.; Ill. Sehr guter Zustand. Leseseiten sind sauber und ohne Markierungen. Buch weist leichte Lagerspuren auf. Sonst sehr gutes Exemplar. 9783835100459 Sprache: Deutsch Gewicht in Gramm: 1100.

Condition: As New. Unread book in perfect condition.

Condition: very good. Broschiert. Sofortversand aus Deutschland. Artikel wiegt maximal 1000g. Bibliotheksexemplar mit Stempel und Kleber. 439 Seiten.