Gpu Expert Engineering: Mastering Design, Programming, and Optimization (21 results)
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Published by Independently Published Jul 2026, 2026
Series: Book 2 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
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Paperback. Condition: new. Paperback. Modern GPU Architecture - Volume 1: Foundations and the Graphics PipelineMost GPU books stop at the surface.They explain shaders, APIs, rendering concepts, or CUDA programming - but they rarely show how the machine underneath actually works.This book goes deeper.Modern GPU Architecture - Vol…ume 1 is written for readers who want to understand the GPU as hardware: how geometry becomes pixels, how SIMT execution hides latency, how shader cores schedule work, how rasterizers make coverage decisions, how memory systems feed thousands of parallel lanes, and how the render-output pipeline commits the final image.This is not a light overview of graphics programming.It is a hardware-focused guide to the architecture behind the graphics pipeline, backed by synthesizable Verilog and SystemVerilog examples that connect theory to real digital design structures.Inside Volume 1, you will learn how GPUs are built from the inside out: Why GPUs favor throughput over single-thread latencyHow SIMT execution groups scalar threads into warps and wavefrontsHow divergence, masking, reconvergence, and scheduling affect real utilizationHow Verilog and SystemVerilog express synthesizable GPU hardwareHow valid-ready handshakes, pipelines, CDC logic, FIFOs, and testbenches work in RTLHow 3D geometry, transformations, clipping, and rasterization become hardware datapathsHow triangle setup, edge functions, fixed-point arithmetic, and tile-based scan conversion operateHow fragment processing, texturing, filtering, blending, and depth testing fit into the pipelineHow shader cores organize schedulers, register files, execution lanes, divergence control, and instruction flowHow GPU memory subsystems handle coalescing, shared memory, L1/L2 caches, DRAM controllers, and atomic operationsHow the render-output pipeline performs depth/stencil testing, blending, MSAA resolve, compression, and framebuffer writebackThis book is for you if you are: An FPGA or RTL hobbyist who wants to build and understand GPU-like hardwareA computer engineering student who wants more than textbook CPU architectureA graphics programmer who understands shaders and wants to know what the silicon is doingA CUDA, HPC, or AI performance reader who wants to understand the layer beneath the software stackAn early-career ASIC, RTL, or verification engineer looking for a clear architectural map of GPU pipeline hardwareThe difference is simple: Most resources tell you what the GPU does.This book shows you how the GPU is organized to do it.From throughput-first design philosophy to shader-core control logic, from rasterization mathematics to fixed-point hardware, from memory coalescing to render-output behavior, Modern GPU Architecture - Volume 1 gives you the architectural foundation needed to read a GPU as an engineer rather than as a user.If you want a shallow introduction, this is not it.If you want to understand the graphics pipeline as real hardware - with RTL concepts, datapaths, control signals, scheduling logic, memory hierarchy, and verification discipline - this volume was written for you.Start with Volume 1 and build the foundation: the complete geometry-to-pixels path of modern GPU architecture. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 2 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
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Paperback. Condition: new. Paperback. Modern GPU Architecture - Volume 2: Acceleration, Integration, and Physical DesignA modern GPU is no longer just a graphics processor.It is a compute engine, AI accelerator, ray-tracing machine, video processor, interconnect fabric, synchronization system, thermal design problem, and silicon… product - all in one.Volume 1 showed how the graphics pipeline becomes hardware.Volume 2 shows how that hardware becomes a complete modern GPU.This volume moves beyond the geometry-to-pixels pipeline and into the accelerators, system engines, performance limits, and physical-design realities that define modern GPU architecture.If you want to understand compute dispatch, tensor cores, ray-tracing units, synchronization, memory ordering, advanced rendering, video engines, interconnects, performance counters, timing closure, packaging, and emerging accelerator design, this book connects them into one coherent system.Inside Volume 2, you will learn: How GPU compute architecture launches and schedules massively parallel kernelsHow occupancy, registers, shared memory, warp slots, and barriers limit resident workHow tensor and matrix accelerators use tiling, systolic datapaths, mixed precision, and sparsityHow ray-tracing hardware performs BVH traversal, primitive testing, ray scheduling, and shader integrationHow barriers, fences, atomics, cache coherence, and memory ordering preserve correctnessHow mesh shaders, VRS, deferred rendering, display engines, video engines, and interconnects fit into the larger GPUHow counters, roofline limits, workload signatures, power, and thermals shape performanceHow floorplanning, synthesis, timing closure, place-and-route, DFT, packaging, and chiplet integration turn architecture into siliconWhere GPU architecture is heading as AI accelerators, new memory systems, and post-Moore scaling reshape the fieldThis book is for readers who want the layer beneath the marketing terms.Not just "tensor cores are fast," but how matrix acceleration changes datapaths, precision, memory layout, and scheduling.Not just "ray tracing uses RT cores," but how traversal, primitive intersections, coherence, sorting, and shader handoff fit into hardware.Not just "GPUs are massively parallel," but how synchronization, resource allocation, interconnect congestion, and thermal limits decide whether that parallelism survives.This book is for you if you are: A hardware or computer-engineering student moving beyond CPU architectureAn FPGA, RTL, or ASIC learner studying GPU-like designA graphics programmer who wants to understand the silicon behind modern renderingA CUDA, HPC, or AI performance reader who wants the hardware layer below kernels and librariesAn early-career engineer who wants a map of how GPU blocks connect, scale, and become manufacturableMost books explain one slice of the GPU.This volume connects the slices.Compute, tensor acceleration, ray tracing, synchronization, rendering, video, interconnect, performance, physical design, and future accelerator trends are treated as parts of one machine - not isolated buzzwords.If Volume 1 is the graphics pipeline foundation, Volume 2 is the complete systems view.Read it to understand how acceleration, integration, and physical design turn modern GPU architecture into real silicon. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 6 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
- Softcover
- Print on Demand
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Paperback. Condition: new. Paperback. Advanced GPU Assembly ProgrammingMost GPU performance problems are not source-code problems. They are machine-code problems.A kernel can look clean in CUDA or HIP and still lose the war at the hardware level.The compiler may choose an instruction sequence you did not expect. A branch may spl…it a warp or wavefront into masked paths. A load pattern may explode into extra memory transactions. A tensor pipeline may sit underfed while the code looks "mathematically right." Occupancy may look healthy while register pressure, wait states, barriers, cache behavior, or issue slots quietly cap throughput.That is where this book begins.Advanced GPU Assembly Programming is for advanced CUDA, HIP, AI-systems, HPC, and compiler engineers who need to read GPU machine code, understand NVIDIA and AMD execution behavior, and push kernels closer to the hardware performance ceiling.This is not an introductory CUDA book.It is not a beginner HIP guide.It is not another surface-level explanation of "parallel programming on GPUs."This is a low-level technical reference for engineers who already understand kernels and now need to understand what those kernels become after compilation.If you are optimizing AI inference, LLM kernels, GEMM, attention, scientific workloads, compiler output, CUDA-to-HIP portability, or architecture-specific performance, the question is no longer: "Does the kernel run?"The question is: What is the machine actually doing, and how close is it to the real limit?Inside, you will learn how to reason about: SIMT execution: warps, wavefronts, active masks, divergence, reconvergence, predication, and independent thread schedulingMachine code: PTX, SASS, AMD ISA, instruction encoding, disassembly, source correlation, and compiler idiomsExecution resources: SMs, CUs, schedulers, issue slots, scoreboards, barriers, wait states, register files, and occupancy limitsMemory behavior: coalescing, global memory, shared memory, LDS, cache policy, HBM bandwidth, alignment, sectors, and bank conflictsTensor and matrix pipelines: tensor cores, MMA, MFMA, TMEM, FP8, FP6, FP4, block scaling, operand staging, and accumulator flowAsynchronous execution: cp.async, tensor-memory movement, producer/consumer roles, barriers, staged pipelines, and latency hidingPerformance evidence: Nsight Compute, Nsight Systems, rocprof, Radeon GPU Profiler, Omniperf, roofline analysis, and microbenchmarkingReal workloads: high-performance GEMM, attention, reductions, scans, sparse computation, atomics, scatter/gather, and irregular kernelsThe value of this book is not that it tells you GPUs are fast.You already know that.The value is that it gives you the machinery to diagnose why a kernel is not fast enough.Why did the compiler emit that instruction sequence?Why did this memory access pattern create extra traffic?Why are tensor units idle?Why did a theoretically good tiling strategy lose throughput?Why did NVIDIA and AMD behave differently?Why did a change that looked harmless at source level move the bottleneck somewhere else?This book helps you connect source code, compiler decisions, disassembly, profiler counters, memory transactions, lane masks, and architectural constraints into one coherent performance model.Advanced GPU Assembly Programming was written for the engineer who wants the layer beneath CUDA, HIP, Triton, compiler output, and vendor libraries. This item is printed on demand. Shipping may be from multiple locations in the US or from the UK, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 1 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
- Softcover
- Print on Demand
Seller: CitiRetail, Stevenage, United KingdomCitiRetail
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Paperback. Condition: new. Paperback. Modern GPU Architecture - Volume 1: Foundations and the Graphics PipelineMost GPU books stop at the surface.They explain shaders, APIs, rendering concepts, or CUDA programming - but they rarely show how the machine underneath actually works.This book goes deeper.Modern GPU Architecture - Vol…ume 1 is written for readers who want to understand the GPU as hardware: how geometry becomes pixels, how SIMT execution hides latency, how shader cores schedule work, how rasterizers make coverage decisions, how memory systems feed thousands of parallel lanes, and how the render-output pipeline commits the final image.This is not a light overview of graphics programming.It is a hardware-focused guide to the architecture behind the graphics pipeline, backed by synthesizable Verilog and SystemVerilog examples that connect theory to real digital design structures.Inside Volume 1, you will learn how GPUs are built from the inside out: Why GPUs favor throughput over single-thread latencyHow SIMT execution groups scalar threads into warps and wavefrontsHow divergence, masking, reconvergence, and scheduling affect real utilizationHow Verilog and SystemVerilog express synthesizable GPU hardwareHow valid-ready handshakes, pipelines, CDC logic, FIFOs, and testbenches work in RTLHow 3D geometry, transformations, clipping, and rasterization become hardware datapathsHow triangle setup, edge functions, fixed-point arithmetic, and tile-based scan conversion operateHow fragment processing, texturing, filtering, blending, and depth testing fit into the pipelineHow shader cores organize schedulers, register files, execution lanes, divergence control, and instruction flowHow GPU memory subsystems handle coalescing, shared memory, L1/L2 caches, DRAM controllers, and atomic operationsHow the render-output pipeline performs depth/stencil testing, blending, MSAA resolve, compression, and framebuffer writebackThis book is for you if you are: An FPGA or RTL hobbyist who wants to build and understand GPU-like hardwareA computer engineering student who wants more than textbook CPU architectureA graphics programmer who understands shaders and wants to know what the silicon is doingA CUDA, HPC, or AI performance reader who wants to understand the layer beneath the software stackAn early-career ASIC, RTL, or verification engineer looking for a clear architectural map of GPU pipeline hardwareThe difference is simple: Most resources tell you what the GPU does.This book shows you how the GPU is organized to do it.From throughput-first design philosophy to shader-core control logic, from rasterization mathematics to fixed-point hardware, from memory coalescing to render-output behavior, Modern GPU Architecture - Volume 1 gives you the architectural foundation needed to read a GPU as an engineer rather than as a user.If you want a shallow introduction, this is not it.If you want to understand the graphics pipeline as real hardware - with RTL concepts, datapaths, control signals, scheduling logic, memory hierarchy, and verification discipline - this volume was written for you.Start with Volume 1 and build the foundation: the complete geometry-to-pixels path of modern GPU architecture. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 6 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
- Softcover
- Print on Demand
Seller: CitiRetail, Stevenage, United KingdomCitiRetail
Contact seller5-star sellerCondition: New
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Paperback. Condition: new. Paperback. Advanced GPU Assembly ProgrammingMost GPU performance problems are not source-code problems. They are machine-code problems.A kernel can look clean in CUDA or HIP and still lose the war at the hardware level.The compiler may choose an instruction sequence you did not expect. A branch may spl…it a warp or wavefront into masked paths. A load pattern may explode into extra memory transactions. A tensor pipeline may sit underfed while the code looks "mathematically right." Occupancy may look healthy while register pressure, wait states, barriers, cache behavior, or issue slots quietly cap throughput.That is where this book begins.Advanced GPU Assembly Programming is for advanced CUDA, HIP, AI-systems, HPC, and compiler engineers who need to read GPU machine code, understand NVIDIA and AMD execution behavior, and push kernels closer to the hardware performance ceiling.This is not an introductory CUDA book.It is not a beginner HIP guide.It is not another surface-level explanation of "parallel programming on GPUs."This is a low-level technical reference for engineers who already understand kernels and now need to understand what those kernels become after compilation.If you are optimizing AI inference, LLM kernels, GEMM, attention, scientific workloads, compiler output, CUDA-to-HIP portability, or architecture-specific performance, the question is no longer: "Does the kernel run?"The question is: What is the machine actually doing, and how close is it to the real limit?Inside, you will learn how to reason about: SIMT execution: warps, wavefronts, active masks, divergence, reconvergence, predication, and independent thread schedulingMachine code: PTX, SASS, AMD ISA, instruction encoding, disassembly, source correlation, and compiler idiomsExecution resources: SMs, CUs, schedulers, issue slots, scoreboards, barriers, wait states, register files, and occupancy limitsMemory behavior: coalescing, global memory, shared memory, LDS, cache policy, HBM bandwidth, alignment, sectors, and bank conflictsTensor and matrix pipelines: tensor cores, MMA, MFMA, TMEM, FP8, FP6, FP4, block scaling, operand staging, and accumulator flowAsynchronous execution: cp.async, tensor-memory movement, producer/consumer roles, barriers, staged pipelines, and latency hidingPerformance evidence: Nsight Compute, Nsight Systems, rocprof, Radeon GPU Profiler, Omniperf, roofline analysis, and microbenchmarkingReal workloads: high-performance GEMM, attention, reductions, scans, sparse computation, atomics, scatter/gather, and irregular kernelsThe value of this book is not that it tells you GPUs are fast.You already know that.The value is that it gives you the machinery to diagnose why a kernel is not fast enough.Why did the compiler emit that instruction sequence?Why did this memory access pattern create extra traffic?Why are tensor units idle?Why did a theoretically good tiling strategy lose throughput?Why did NVIDIA and AMD behave differently?Why did a change that looked harmless at source level move the bottleneck somewhere else?This book helps you connect source code, compiler decisions, disassembly, profiler counters, memory transactions, lane masks, and architectural constraints into one coherent performance model.Advanced GPU Assembly Programming was written for the engineer who wants the layer beneath CUDA, HIP, Triton, compiler output, and vendor libraries. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 2 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
- Softcover
- Print on Demand
Seller: CitiRetail, Stevenage, United KingdomCitiRetail
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Paperback. Condition: new. Paperback. Modern GPU Architecture - Volume 2: Acceleration, Integration, and Physical DesignA modern GPU is no longer just a graphics processor.It is a compute engine, AI accelerator, ray-tracing machine, video processor, interconnect fabric, synchronization system, thermal design problem, and silicon… product - all in one.Volume 1 showed how the graphics pipeline becomes hardware.Volume 2 shows how that hardware becomes a complete modern GPU.This volume moves beyond the geometry-to-pixels pipeline and into the accelerators, system engines, performance limits, and physical-design realities that define modern GPU architecture.If you want to understand compute dispatch, tensor cores, ray-tracing units, synchronization, memory ordering, advanced rendering, video engines, interconnects, performance counters, timing closure, packaging, and emerging accelerator design, this book connects them into one coherent system.Inside Volume 2, you will learn: How GPU compute architecture launches and schedules massively parallel kernelsHow occupancy, registers, shared memory, warp slots, and barriers limit resident workHow tensor and matrix accelerators use tiling, systolic datapaths, mixed precision, and sparsityHow ray-tracing hardware performs BVH traversal, primitive testing, ray scheduling, and shader integrationHow barriers, fences, atomics, cache coherence, and memory ordering preserve correctnessHow mesh shaders, VRS, deferred rendering, display engines, video engines, and interconnects fit into the larger GPUHow counters, roofline limits, workload signatures, power, and thermals shape performanceHow floorplanning, synthesis, timing closure, place-and-route, DFT, packaging, and chiplet integration turn architecture into siliconWhere GPU architecture is heading as AI accelerators, new memory systems, and post-Moore scaling reshape the fieldThis book is for readers who want the layer beneath the marketing terms.Not just "tensor cores are fast," but how matrix acceleration changes datapaths, precision, memory layout, and scheduling.Not just "ray tracing uses RT cores," but how traversal, primitive intersections, coherence, sorting, and shader handoff fit into hardware.Not just "GPUs are massively parallel," but how synchronization, resource allocation, interconnect congestion, and thermal limits decide whether that parallelism survives.This book is for you if you are: A hardware or computer-engineering student moving beyond CPU architectureAn FPGA, RTL, or ASIC learner studying GPU-like designA graphics programmer who wants to understand the silicon behind modern renderingA CUDA, HPC, or AI performance reader who wants the hardware layer below kernels and librariesAn early-career engineer who wants a map of how GPU blocks connect, scale, and become manufacturableMost books explain one slice of the GPU.This volume connects the slices.Compute, tensor acceleration, ray tracing, synchronization, rendering, video, interconnect, performance, physical design, and future accelerator trends are treated as parts of one machine - not isolated buzzwords.If Volume 1 is the graphics pipeline foundation, Volume 2 is the complete systems view.Read it to understand how acceleration, integration, and physical design turn modern GPU architecture into real silicon. This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.
Language: English
Published by Independently Published, 2026
Series: Book 5 of 6 - GPU Expert Engineering: Mastering Design, Programming, and Optimization
- Softcover
- Print on Demand
Seller: CitiRetail, Stevenage, United KingdomCitiRetail
Contact seller5-star sellerCondition: New
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Paperback. Condition: new. Paperback. Most CUDA programmers never see the real program their GPU actually runs.They write CUDA C++. They launch kernels. They profile. They tune block sizes, adjust memory access, stare at Nsight reports, and hope the compiler has done what they think it has done.But the truth is lower down.The tr…uth is in PTX. The truth is in SASS.Mastering PTX and SASS is for CUDA programmers, GPU performance engineers, ML systems developers, compiler-minded programmers, and high-performance computing specialists who want to understand NVIDIA GPU execution below the source level.This is not a beginner CUDA book.It is for readers who already understand the basic GPU programming model and now want to inspect the layer where performance is really exposed: instruction streams, register allocation, memory transactions, predicate logic, compiler output, synchronization, tensor pipelines, and architecture-specific machine code.Inside, you will learn how to: Understand how CUDA source becomes PTX, and how PTX becomes SASSUse PTX as a portable low-level view of compiler intentUse SASS as evidence of what the GPU actually executesInterpret register pressure, spills, occupancy, instruction scheduling, and memory trafficDiagnose coalescing problems, bank conflicts, branch divergence, dependency stalls, and synchronization costsWork with tensor cores, MMA, WGMMA, TMA, low-precision formats, and modern NVIDIA architecture featuresUse nvcc, ptxas, cuobjdump, nvdisasm, Nsight Compute, Nsight Systems, and Compute Sanitizer as practical engineering toolsDecide when CUDA C++, compiler flags, intrinsics, inline PTX, full PTX, or SASS inspection is the right level to touchThe goal is not assembly for its own sake.The goal is diagnosis.The goal is control.The goal is to look at a slow kernel and know whether the limiting factor is memory movement, instruction throughput, register pressure, tensor-pipeline starvation, branch behavior, synchronization overhead, launch cost, or compiler transformation.Modern GPU performance is not won by writing code that merely runs.It is won by understanding how the machine schedules work, moves data, allocates registers, forms instructions, hides latency, feeds tensor units, and exposes bottlenecks through measurable evidence.This book is for you if you already write CUDA code and want to understand what happens after compilation.If you are still learning what a thread block is or how kernels launch, start with an introductory CUDA book first.But if you want to read below the source level, connect profiler symptoms to architectural causes, and move closer to the real hardware ceiling, Mastering PTX and SASS was written for you.Correctness is only the beginning.The real question is: how close can you get to the hardware ceiling? This item is printed on demand. Shipping may be from our UK warehouse or from our Australian or US warehouses, depending on stock availability.
