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Published by Springer International Publishing, 2015
ISBN 10: 3031006208 ISBN 13: 9783031006203
Language: English
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Add to basketTaschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development oncustomizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems.
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Published by Springer International Publishing Jul 2015, 2015
ISBN 10: 3031006208 ISBN 13: 9783031006203
Language: English
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
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Add to basketTaschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific integrated circuits (ASICs) motivates the exploration of customizable architectures, where one can adapt the architecture to the workload. In this Synthesis lecture, we present an overview and introduction of the recent developments on energy-efficient customizable architectures, including customizable cores and accelerators, on-chip memory customization, and interconnect optimization. In addition to a discussion of the general techniques and classification of different approaches used in each area, we also highlight and illustrate some of the most successful design examples in each category and discuss their impact on performance and energy efficiency. We hope that this work captures the state-of-the-art research and development on customizable architectures and serves as a useful reference basis for further research, design, and implementation for large-scale deployment in future computing systems. 120 pp. Englisch.
Published by Springer, Berlin|Springer International Publishing|Morgan & Claypool|Springer, 2015
ISBN 10: 3031006208 ISBN 13: 9783031006203
Language: English
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Add to basketCondition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Since the end of Dennard scaling in the early 2000s, improving the energy efficiency of computation has been the main concern of the research community and industry. The large energy efficiency gap between general-purpose processors and application-specific.