Routing Congestion in VLSI Circuits
Saxena, Prashant; Shelar, Rupesh S. (Intel Corporation); Sapatnekar, Sachin S.
ISBN 10: 1441940138 ISBN 13: 9781441940131
Published by Springer-Verlag New York Inc., 2010
New
Soft cover
From
Kennys Bookshop and Art Galleries Ltd., Galway, GY, Ireland
Seller rating 5 out of 5 stars
AbeBooks Seller since February 27, 2001
This specific item is no longer available.
About this Item
Description:
This volume provides a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, offers techniques for estimating and relieving congestion, and provides a critical analysis of the accuracy and effectiveness of these techniques. Series: Integrated Circuits and Systems. Num Pages: 250 pages, biography. BIC Classification: TJFC. Category: (P) Professional & Vocational. Dimension: 234 x 156 x 14. Weight in Grams: 409. . 2010. 1st ed. Softcover of orig. ed. 2007. Paperback. . . . . Seller Inventory # V9781441940131
Synopsis:
This volume provides the reader with a complete understanding of the fundamental causes of routing congestion in present-day and next-generation VLSI circuits, techniques for estimating and relieving congestion, and a critical analysis of the accuracy and effectiveness of these techniques. Readers are supplied with the knowledge to prudently choose an approach that is appropriate to their design goals. The book includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing phase. The subjects covered include an explanation of why the problem of congestion is important and how it will trend, plus definitions of metrics that are appropriate for measuring congestion, and descriptions of techniques for estimating and optimizing routing congestion issues in cell-/library-based VLSI circuits.
From the Back Cover:
With the dramatic increases in on-chip packing densities, routing congestion has become a major problem in chip design. The problem is especially acute as interconnects are also the performance bottleneck in integrated circuits. The solution lies in judicious resource management. This involves intelligent allocation of the available interconnect resources, up-front planning of the wire routes for even wire distributions, and transformations that make the physical synthesis flow congestion-aware.
Routing Congestion in VLSI Circuits: Estimation and Optimization provides the reader with a complete understanding of the root causes of routing congestion in present-day and future VLSI circuits, available techniques for estimating and optimizing this congestion, and a critical analysis of the accuracy and effectiveness of these techniques, so that the reader may prudently choose an approach that is appropriate to their design goals. The scope of the work includes metrics and optimization techniques for routing congestion at various stages of the VLSI design flow, including the architectural level, the logic synthesis/technology mapping level, the placement phase, and the routing step. A particular focus of this work is on the congestion issues that deal primarily with standard cell based design.
Routing Congestion in VLSI Circuits: Estimation and Optimization is a valuable reference for CAD developers and researchers, design methodology engineers, VLSI design and CAD students, and VLSI design engineers.
"About this title" may belong to another edition of this title.
Bibliographic Details
Title: Routing Congestion in VLSI Circuits
Publisher: Springer-Verlag New York Inc.
Publication Date: 2010
Binding: Soft cover
Condition: New
Edition: 1st Edition
Top Search Results from the AbeBooks Marketplace
Stock Image
Routing Congestion in VLSI Circuits (Paperback)
Published by
Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10: 1441940138
ISBN 13: 9781441940131
New
Paperback
First Edition
Seller: Grand Eagle Retail, Bensenville, IL, U.S.A.
Seller rating 5 out of 5 stars
Paperback. Condition: new. Paperback. With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid tra?c jams; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow. With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9781441940131
Quantity: 1 available
Stock Image
Routing Congestion in VLSI Circuits (Paperback)
Published by
Springer-Verlag New York Inc., New York, NY, 2010
ISBN 10: 1441940138
ISBN 13: 9781441940131
New
Paperback
First Edition
Seller: AussieBookSeller, Truganina, VIC, Australia
Seller rating 5 out of 5 stars
Paperback. Condition: new. Paperback. With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. The problem is especially acute as interconnects are becoming the performance bottleneck in modern integrated circuits. Even with more than 30% of white space, some of the design blocks in modern microprocessor and ASIC designs cannot be routed successfully. Moreover, this problem is likely to worsen considerably in the coming years due to design size and technology scaling. There is an inherent tradeo? between choosing a minimum delay path for interconnect nets, and the need to detour the routes to avoid tra?c jams; congestion management involves intelligent allocation of the available int- connect resources, up-front planning of the wire routes for even distributions, and transformations that make the physical synthesis ?ow congestion-aware. The book explores this tradeo? that lies at the heart of all congestion m- agement, in seeking to address the key question: how does one optimize the traditional design goals such as the delay or the area of a circuit, while still ensuring that the circuit remains routable? It begins by motivating the c- gestion problem, explaining why this problem is important and how it will trend. It then progresses with comprehensive discussions of the techniques available for estimating and optimizing congestion at various stages in the design ?ow. With dramatic increases in on-chip packing densities, routing congestion has become a major problem in integrated circuit design, impacting convergence, performance, and yield, and complicating the synthesis of critical interc- nects. Shipping may be from our Sydney, NSW warehouse or from our UK or US warehouse, depending on stock availability. Seller Inventory # 9781441940131
Quantity: 1 available