Fault Tolerance Through Self-configuration in Nanoscale Processors - Softcover

Zajac, Piotr

Softcover

ISBN 10: 3639202740 ISBN 13: 9783639202748

Publisher: Vdm Verlag Dr Mueller E K, 2009

Synopsis

This work is a contribution at the architectural level to the improvement of fault tolerance in massively defective multicore chips fabricated using nanometer transistors. The main idea of this work is that a chip should be organized in a replicated architecture and become as autonomous as possible to increase its resilience against both permanent defects and transient faults occurring at runtime. Therefore, we introduce a new chip self-configuration methodology, which allows detecting and isolating the defective cores, deactivating the isolated cores, configuring the communications between the cores and managing the allocation and execution of tasks. The efficiency of the proposed methods is studied as a function of the fraction of defective cores, the fraction of defective interconnects and the soft error rate.

Edition details

• Publisher: Vdm Verlag Dr Mueller E K
• Publication date: 2009
• Language: English
• ISBN 10: 3639202740
• ISBN 13: 9783639202748
• Binding: Paperback
• Number of pages: 164