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Nanometer Technology Designs: High-Quality Delay Tests (Frontiers in Electronic Testing) - Hardcover
Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test.
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While adopting newer, better fabrication technologies provides higher integration and enhances performance, it also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz, timing-related defects have become a high proportion of the total chip defects. For nanometer technology designs, the traditional test methods cannot ensure a high quality level of chips, and at-speed tests using path and transition delay fault model have become a requirement in technologies below 180nm.
Nanometer Technology Designs: High-Quality Delay Tests discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the delay test for nanotechnology designs. Topics covered include:
- At-speed test challenges for nanotechnology
- Low-cost tester-friendly design-for-test techniques
- Improving test quality of current at-speed test methods
- Functionally un-testable fault list generation and avoidance
- Timing-based ATPG for screening small delay faults
- Faster-than-at-speed test considering power supply noise
- Power supply noise tolerant at-speed test pattern generation and application
- Solutions for dealing with crosstalk and signal integrity issues
Nanometer Technology Designs: High-Quality Delay Tests is a reference for practicing engineers and researchers in both industry and academia who are interested in learning about and implementing the most-advanced methods in nanometer delay testing.
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- PublisherSpringer
- Publication date2007
- ISBN 10 0387764860
- ISBN 13 9780387764863
- BindingHardcover
- Number of pages299
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Nanometer Technology Designs: High-Quality Delay Tests (Frontiers in Electronic Testing) by Ahmed, Nisar [Hardcover ]
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Nanometer Technology Designs: High-Quality Delay Tests (Frontiers in Electronic Testing)
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Nanometer Technology Designs: High-Quality Delay Tests
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Nanometer Technology Designs
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Book Description Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise effects on chip performance, high test pattern volume, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test. 304 pp. Englisch. Seller Inventory # 9780387764863
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Book Description Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Identifies defects in traditional at-speed test methodsProposes new techniques and methodologes to improve the overall quality of transition fault testsIncludes discussion of the effects of IR-dropProvides an introduction to path del. Seller Inventory # 5911034
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Nanometer Technology Designs : High-Quality Delay Tests
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ISBN 10: 0387764860
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Book Description Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Adopting new fabrication technologies not only provides higher integration and enhances performance, but also increases the types of manufacturing defects. With design size in millions of gates and working frequency in GHz timing-related defects havv become a high proportion of the total chip defects. For nanometer technology designs, the stuck-at fault test alone cannot ensure a high quality level of chips. At-speed tests using the transition fault model has become a requirement in technologies below 180nm.Traditional at-speed test methods cannot guarantee high quality test results as they face many new challenges. Supply noise (including IR-drop, ground bounce, and Ldi/dt) effects on chip performance, high test pattern volume, low fault/defect coverage, small delay defect test pattern generation, high cost of test implementation and application, and utilizing low-cost testers are among these challenges. This book discusses these challenges in detail and proposes new techniques and methodologies to improve the overall quality of the transition fault test. Seller Inventory # 9780387764863
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