Items related to Testing Semiconductor Memories: Theory and Practice
Synopsis
Goor (EE, Delft U.) presents memory test models on the chip, array, and board level. For each a class of fault models is introduced together with opposite tests. He particularly stresses the appropriateness of fault models to their class. Annotation copyright Book News, Inc. Portland, Or.
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From the Publisher
As the size and density of semiconductor memories are increasing rapidly, testing them is becoming a major concern. This book tries to bring order to the vast amount of material published in the field by introducing a framework for ordering fault models and covering those test algorithms which are considered most efficient for finding the faults of each fault model. It presents memory test problems on the chip, array and board level, introducing fault models and tests for them at each of those levels.
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Testing Semiconductor Memories: Theory and Practice
Seller: Austin Goodwill 1101, Austin, TX, U.S.A.
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Condition: good. Book shows general signs of use and handling. May have light wear on the cover or edges and minimal writing or highlighting. Binding remains tight, and pages are clean and readable. Seller Inventory # CTXV.0471925861.G
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Testing Semiconductor Memories : Theory and Practice
Published by
Wiley & Sons, Incorporated, John, 1991
ISBN 10: 0471925861
ISBN 13: 9780471925866
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Testing Semiconductor Memories: Theory and Practice
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Testing Semiconductor Memories: Theory and Practice
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hardcover. Condition: New. In shrink wrap. Looks like an interesting title! Seller Inventory # Q-0471925861
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Testing Semiconductor Memories: Theory and Practice
Published by
Somerset, New Jersey, U.S.A.: John Wiley & Sons Inc, 1991
ISBN 10: 0471925861
ISBN 13: 9780471925866
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Hardcover
First Edition
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Hardcover. Condition: Near Fine. No Jacket. 1st Edition. hardback book in near fine condition,motorola-employee name at top of first blank page. Seller Inventory # 85700