Testing Semiconductor Memories: Theory and Practice - Hardcover

Van De Goor, A. J.

Hardcover

ISBN 10: 0471925861 ISBN 13: 9780471925866

Publisher: John Wiley & Sons Inc, 1998

Synopsis

Goor (EE, Delft U.) presents memory test models on the chip, array, and board level. For each a class of fault models is introduced together with opposite tests. He particularly stresses the appropriateness of fault models to their class. Annotation copyright Book News, Inc. Portland, Or.

About this title

From the Publisher:

As the size and density of semiconductor memories are increasing rapidly, testing them is becoming a major concern. This book tries to bring order to the vast amount of material published in the field by introducing a framework for ordering fault models and covering those test algorithms which are considered most efficient for finding the faults of each fault model. It presents memory test problems on the chip, array and board level, introducing fault models and tests for them at each of those levels.

About this edition

• Publisher: John Wiley & Sons Inc
• Publication date: 1998
• ISBN 10: 0471925861
• ISBN 13: 9780471925866
• Binding: Hardcover
• Number of pages: 512