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Goor (EE, Delft U.) presents memory test models on the chip, array, and board level. For each a class of fault models is introduced together with opposite tests. He particularly stresses the appropriateness of fault models to their class. Annotation copyright Book News, Inc. Portland, Or.
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As the size and density of semiconductor memories are increasing rapidly, testing them is becoming a major concern. This book tries to bring order to the vast amount of material published in the field by introducing a framework for ordering fault models and covering those test algorithms which are considered most efficient for finding the faults of each fault model. It presents memory test problems on the chip, array and board level, introducing fault models and tests for them at each of those levels.
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Book Description John Wiley & Sons Inc, 1998. Hardcover. Condition: New. Never used!. Seller Inventory # P110471925861