Low Power Design in Deep Submicron Electronics (NATO Science Series E:, 337) - Hardcover

Hardcover

ISBN 10: 079234569X ISBN 13: 9780792345695

Publisher: Springer, 1997

Synopsis

Decreasing power dissipation per logic function has become a primary concern in virtually all CMOS system chips designed today as a result of the relentless progress in processing technology that has led us into the deep-submicron age. Evolution from 1 micron to 0.1 micron lithography in the next decade will not be possible without a change in the way we design CMOS systems. But power reduction requires an overall optimisation, ranging from software compilation over instruction set design down to the introduction of much more parallelism in the architecture, the optimal use of memory hierarchy, new clocking strategies, use of asynchronous techniques, new CMOS circuit techniques and management of leakage currents in new low power technologies. Moreover, performance and power dissipation will come to be dominated by interconnect and thus completely new floor planning and place and route strategies are emerging.
The chapters in this book present a systematic coverage of deep submicron CMOS digital system design for low power, from process technology all the way up to software design and embedded software systems.
Audience: An excellent guide for the practising engineer, researcher and student interested in this crucial aspect of actual CMOS design.

About this edition

• Publisher: Springer
• Publication date: 1997
• ISBN 10: 079234569X
• ISBN 13: 9780792345695
• Binding: Hardcover
• Number of pages: 600
• Editor: Nebel W., Mermet Jean