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Delay Fault Testing for VLSI Circuits (Frontiers in Electronic Testing, 14) - Hardcover
Book 31 of 40: Frontiers in Electronic Testing
Synopsis
In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.
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Delay Fault Testing for VLSI Circuits
Published by
Kluwer Academic Pub, Boston, 1998
ISBN 10: 0792382951
ISBN 13: 9780792382959
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Delay Fault Testing for VLSI Circuits (Frontiers in Electronic Testing, 14)
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Delay Fault Testing for VLSI Circuits
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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest. 212 pp. Englisch. Seller Inventory # 9780792382959
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Delay Fault Testing for VLSI Circuits
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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, o. Seller Inventory # 5970813
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Delay Fault Testing for VLSI Circuits
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Condition: Sehr gut. Zustand: Sehr gut | Sprache: Englisch | Produktart: Bücher | In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest. Seller Inventory # 3023274/202
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Delay Fault Testing for VLSI Circuits
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Delay Fault Testing for VLSI Circuits
Published by
Kluwer Academic Publishers, 1998
ISBN 10: 0792382951
ISBN 13: 9780792382959
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Condition: New. Presents a selection of existing delay testing research results. This book combines introductory material with techniques that address some of the problems in delay testing. It covers some basic topics such as fault modeling and test application schemes for detecting delay defects. Series: Frontiers in Electronic Testing. Num Pages: 203 pages, biography. BIC Classification: TJFD; UY. Category: (P) Professional & Vocational; (UP) Postgraduate, Research & Scholarly. Dimension: 234 x 156 x 12. Weight in Grams: 1050. . 1998. Hardback. . . . . Seller Inventory # V9780792382959
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Delay Fault Testing for VLSI Circuits
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Buch. Condition: Neu. Delay Fault Testing for VLSI Circuits | Kwang-Ting Cheng (u. a.) | Buch | Einband - fest (Hardcover) | Englisch | 1998 | Springer US | EAN 9780792382959 | Verantwortliche Person für die EU: Springer Heidelberg, Tiergartenstr. 17, 69121 Heidelberg, buchhandel-buch[at]springer[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 102549225
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Delay Fault Testing for VLSI Circuits
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Condition: New. Print on Demand pp. 212 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Seller Inventory # 7559574
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Delay Fault Testing for VLSI Circuits
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Springer US, Springer US Okt 1998, 1998
ISBN 10: 0792382951
ISBN 13: 9780792382959
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Buch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 212 pp. Englisch. Seller Inventory # 9780792382959
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