Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science, 289) - Hardcover
Synopsis
Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.
The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure.
Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.
"synopsis" may belong to another edition of this title.
Other Popular Editions of the Same Title
Search results for Modeling of Electrical Overstress in Integrated Circuits...
Stock Image
Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science, 289)
Seller: BennettBooksLtd, Los Angeles, CA, U.S.A.
Seller rating 5 out of 5 stars
hardcover. Condition: New. In shrink wrap. Looks like an interesting title! Seller Inventory # Q-0792395050
Stock Image
Modeling of Electrical Overstress in Integrated Circuits (The Springer International Series in Engineering and Computer Science, 289)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In. Seller Inventory # ria9780792395058_new
Buy New
US$ 191.03
US$ 16.12 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: Over 20 available
Seller Image
Modeling of Electrical Overstress in Integrated Circuits
Print on DemandSeller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Ele. Seller Inventory # 5971543
Buy New
US$ 163.19
US$ 57.01 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: Over 20 available
Stock Image
Modeling of Electrical Overstress in Integrated Circuits
Seller: Books Puddle, New York, NY, U.S.A.
Seller rating 4 out of 5 stars
Condition: New. pp. 180. Seller Inventory # 263069774
Seller Image
Modeling of Electrical Overstress in Integrated Circuits
Print on DemandSeller: preigu, Osnabrück, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. Modeling of Electrical Overstress in Integrated Circuits | Carlos H. Diaz (u. a.) | Buch | xxv | Englisch | 1994 | Springer | EAN 9780792395058 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 102548891
Buy New
US$ 169.24
US$ 81.46 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: 5 available
Stock Image
Modeling of Electrical Overstress in Integrated Circuits
Print on DemandSeller: Majestic Books, Hounslow, United Kingdom
Seller rating 4 out of 5 stars
Condition: New. Print on Demand pp. 180 52:B&W 6.14 x 9.21in or 234 x 156mm (Royal 8vo) Case Laminate on White w/Gloss Lam. Seller Inventory # 5859473
Buy New
US$ 245.38
US$ 8.75 shipping
Ships from United Kingdom to U.S.A.
Ships from United Kingdom to U.S.A.
Quantity: 4 available
Seller Image
Modeling of Electrical Overstress in Integrated Circuits
Published by
Springer, Springer Nov 1994, 1994
ISBN 10: 0792395050
ISBN 13: 9780792395058
New
Hardcover
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits.The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure.Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 178 pp. Englisch. Seller Inventory # 9780792395058
Buy New
US$ 192.35
US$ 69.82 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: 1 available
Seller Image
Modeling of Electrical Overstress in Integrated Circuits
Print on DemandSeller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields. 178 pp. Englisch. Seller Inventory # 9780792395058
Buy New
US$ 243.61
US$ 26.76 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: 2 available
Seller Image
Modeling of Electrical Overstress in Integrated Circuits
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Electrical overstress (EOS) and Electrostatic discharge (ESD) pose one of the most dominant threats to integrated circuits (ICs). These reliability concerns are becoming more serious with the downward scaling of device feature sizes. Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS/ESD-related failures in I/O protection devices in integrated circuits. The design of I/O protection circuits has been done in a hit-or-miss way due to the lack of systematic analysis tools and concrete design guidelines. In general, the development of on-chip protection structures is a lengthy expensive iterative process that involves tester design, fabrication, testing and redesign. When the technology is changed, the same process has to be repeated almost entirely. This can be attributed to the lack of efficient CAD tools capable of simulating the device behavior up to the onset of failure which is a 3-D electrothermal problem. For these reasons, it is important to develop and use an adequate measure of the EOS robustness of integrated circuits in order to address the on-chip EOS protection issue. Fundamental understanding of the physical phenomena leading to device failures under ESD/EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure. Modeling of Electrical Overstress in Integrated Circuits is for VLSI designers and reliability engineers, particularly those who are working on the development of EOS/ESD analysis tools. CAD engineers working on development of circuit level and device level electrothermal simulators will also benefit from the material covered. This book will also be of interest to researchers and first and second year graduate students working in semiconductor devices and IC reliability fields. Seller Inventory # 9780792395058
Buy New
US$ 200.32
US$ 72.38 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: 1 available
Stock Image
Modeling of Electrical Overstress in Integrated Circuits
Print on DemandSeller: Biblios, Frankfurt am main, HESSE, Germany
Seller rating 4 out of 5 stars
Condition: New. PRINT ON DEMAND pp. 180. Seller Inventory # 183069764
Buy New
US$ 262.80
US$ 11.58 shipping
Ships from Germany to U.S.A.
Ships from Germany to U.S.A.
Quantity: 4 available