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Synopsis
HyperTransportTM technology has revolutionized microprocessor core interconnect. It serves as the central interconnect technology for nearly all of AMD s microprocessors as well as for a rich ecosystem of other microprocessors, system controllers, graphics processors, network processors, and communications semiconductors. It is a high-speed, low latency, point-to-point, packetized link. The latest version, HyperTransport 3.1, enables data transfer at rates of up to 51.2 GigaBytes per second. It is scalable, error tolerant, and designed for ease of use. It is also compatible with PCIe, PCI-X, PCI, and AGP buses and includes comprehensive power management and x86 platform support. The HTX and HTX3 specifications define a PC architecture I/O slot that provides the lowest latency slot access to a microprocessor available. HyperTransport 3.1 Interconnect provides a comprehensive guide to all of the releases of HyperTransport technology, from 1.03, through 2.0, to 3.1. This book includes over 250 drawings and over 100 tables.
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About the Author
Brian Holden has been the Technical Chair of the HyperTransport Consortium since 2002, serves as its V.P. and Acting President, and was made a Fellow in 2006. He was a co-founder of StrataCom, has served in CEO, CTO & Director roles in the communications semiconductor and microprocessor industries, and holds 17 U.S. patents.
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HyperTransport 3.1 Interconnect Technology
Seller: Recycle Bookstore, San Jose, CA, U.S.A.
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Paperback. Condition: Fine. This book has very light wear around the edges, otherwise it is in great condition and looks almost as new. Seller Inventory # 909421
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