Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)

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9781461359821: Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)

Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.
The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.

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Jeong-Taek Kong, David V. Overhauser
Published by Springer-Verlag New York Inc., United States (2012)
ISBN 10: 1461359821 ISBN 13: 9781461359821
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Book Description Springer-Verlag New York Inc., United States, 2012. Paperback. Book Condition: New. 235 x 155 mm. Language: English . Brand New Book ***** Print on Demand *****.Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Softcover reprint of the original 1st ed. 1995. Bookseller Inventory # AAV9781461359821

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Jeong-Taek Kong, David V. Overhauser
Published by Springer-Verlag New York Inc., United States (2012)
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Book Description Springer-Verlag New York Inc., United States, 2012. Paperback. Book Condition: New. 235 x 155 mm. Language: English . Brand New Book ***** Print on Demand *****. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Softcover reprint of the original 1st ed. 1995. Bookseller Inventory # AAV9781461359821

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Book Description Springer-Verlag New York Inc., 2012. PAP. Book Condition: New. New Book. Delivered from our UK warehouse in 3 to 5 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Bookseller Inventory # LQ-9781461359821

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Book Description Springer-Verlag New York Inc., 2012. PAP. Book Condition: New. New Book. Shipped from US within 10 to 14 business days. THIS BOOK IS PRINTED ON DEMAND. Established seller since 2000. Bookseller Inventory # IQ-9781461359821

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Book Description Springer, 2016. Paperback. Book Condition: New. PRINT ON DEMAND Book; New; Publication Year 2016; Not Signed; Fast Shipping from the UK. No. book. Bookseller Inventory # ria9781461359821_lsuk

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Book Description Springer, 2012. Paperback. Book Condition: NEW. 9781461359821 This listing is a new book, a title currently in-print which we order directly and immediately from the publisher. Bookseller Inventory # HTANDREE0413915

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Kong, Jeong-Taek; Overhauser, David V.
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Book Description Springer, 2012. Paperback. Book Condition: Brand New. reprint edition. 9.20x6.10 inches. In Stock. Bookseller Inventory # __1461359821

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