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Constraining Designs for Synthesis and Timing Analysis: A Practical Guide to Synopsys Design Constraints (SDC) - Softcover
About the Author
Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.
Sridhar Gangadharan is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.
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- PublisherSpringer
- ISBN 10 1461432707
- ISBN 13 9781461432708
- BindingPaperback
- LanguageEnglish
- Number of pages256
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