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Synopsis
This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic.
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- PublisherSpringer
- Publication date2013
- ISBN 10 1461494044
- ISBN 13 9781461494041
- BindingHardcover
- LanguageEnglish
- Number of pages156
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Source-Synchronous Networks-On-Chip : Circuit and Architectural Interconnect Modeling
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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling
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Source-Synchronous Networks-On-Chip
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Springer New York Nov 2013, 2013
ISBN 10: 1461494044
ISBN 13: 9781461494041
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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. 160 pp. Englisch. Seller Inventory # 9781461494041
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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling
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Source-Synchronous Networks-On-Chip : Circuit and Architectural Interconnect Modeling
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Springer New York, Springer US, 2013
ISBN 10: 1461494044
ISBN 13: 9781461494041
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Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes novel methods for network-on-chip (NoC) design, using source-synchronous high-speed resonant clocks. The authors discuss NoCs from the bottom up, providing circuit level details, before providing architectural simulations. As a result, readers will get a complete picture of how a NoC can be designed and optimized. Using the methods described in this book, readers are enabled to design NoCs that are 5X better than existing approaches in terms of latency and throughput and can also sustain a significantly greater amount of traffic. Seller Inventory # 9781461494041
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Source-Synchronous Networks-On-Chip
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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Describes novel methods for high-speed network-on-chip (NoC) design Enables readers to understand NoC design from both circuit and architectural levels Provides circuit-level details of the NoC (including clocking, router design), along wit. Seller Inventory # 4199984
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Source-Synchronous Networks-On-Chip: Circuit and Architectural Interconnect Modeling
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ISBN 10: 1461494044
ISBN 13: 9781461494041
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Source-Synchronous Networks-On-Chip
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Source-Synchronous Networks-On-Chip
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Source-Synchronous Networks-on-Chip: Circuit and Architectural Interconnect Modeling
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Hardcover. Condition: Brand New. 143 pages. 9.25x6.50x0.75 inches. In Stock. Seller Inventory # x-1461494044
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