Items related to Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold...
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction (The Springer International Series in Engineering and Computer Science) - Softcover
Synopsis
1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as "Moore's Law" and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance.
"synopsis" may belong to another edition of this title.
- PublisherSpringer
- Publication date2012
- ISBN 10 1475710577
- ISBN 13 9781475710571
- BindingPaperback
- LanguageEnglish
- Number of pages168
Buy New
View this item
US$ 70.24
US$ 16.08 shipping from United Kingdom to U.S.A.
Destination, rates & speedsOther Popular Editions of the Same Title
Search results for Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold...
Stock Image
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction (The Springer International Series in Engineering and Computer Science)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In. Seller Inventory # ria9781475710571_new
Quantity: Over 20 available
Stock Image
Low-Power Deep Sub-Micron Cmos Logic (The Springer International Series in Engineering and Computer Science)
Seller: Chiron Media, Wallingford, United Kingdom
Seller rating 5 out of 5 stars
Paperback. Condition: New. Seller Inventory # 6666-IUK-9781475710571
Quantity: 10 available
Stock Image
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction
Published by
Springer-Verlag New York Inc., 2012
ISBN 10: 1475710577
ISBN 13: 9781475710571
New
Paperback / softback
Seller: THE SAINT BOOKSTORE, Southport, United Kingdom
Seller rating 5 out of 5 stars
Paperback / softback. Condition: New. This item is printed on demand. New copy - Usually dispatched within 5-9 working days 302. Seller Inventory # C9781475710571
Quantity: Over 20 available
Seller Image
Low-Power Deep Sub-Micron CMOS Logic : Sub-threshold Current Reduction
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - 1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as 'Moore's Law' and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase.In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance. Seller Inventory # 9781475710571
Quantity: 1 available
Seller Image
Low-Power Deep Sub-Micron CMOS Logic
Print on DemandSeller: moluna, Greven, Germany
Seller rating 5 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Classifies all power dissipation sources in digital CMOS circuitsProvides for a systematic approach of power reduction techniquesA clear distinction between power dissipated to perform a calculation in a certain time frame, i.e. functional . Seller Inventory # 4206973
Quantity: Over 20 available
Seller Image
Low-Power Deep Sub-Micron CMOS Logic
Print on DemandSeller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -1. 1 Power-dissipation trends in CMOS circuits Shrinking device geometry, growing chip area and increased data-processing speed performance are technological trends in the integrated circuit industry to enlarge chip functionality. Already in 1965 Gordon Moore predicted that the total number of devices on a chip would double every year until the 1970s and every 24 months in the 1980s. This prediction is widely known as 'Moore's Law' and eventually culminated in the Semiconductor Industry Association (SIA) technology road map [1]. The SIA road map has been a guide for the in dustry leading them to continued wafer and die size growth, increased transistor density and operating frequencies, and defect density reduction. To mention a few numbers; the die size increased 7% per year, the smallest feature sizes decreased 30% and the operating frequencies doubled every two years. As a consequence of these trends both the number of transistors and the power dissi pation per unit area increase. In the near future the maximum power dissipation per unit area will be reached. Down-scaling of the supply voltage is not only the most effective way to reduce power dissipation in general it also is a necessary precondition to ensure device reliability by reducing electrical fields and device temperature, to prevent device degradation. A draw-back of this solution is an increased signal propa gation delay, which results in a lower data-processing speed performance. 172 pp. Englisch. Seller Inventory # 9781475710571
Quantity: 2 available
Stock Image
Low-Power Deep Sub-Micron CMOS Logic: Sub-threshold Current Reduction (The Springer International Series in Engineering and Computer Science (841))
Seller: Mispah books, Redhill, SURRE, United Kingdom
Seller rating 4 out of 5 stars
Paperback. Condition: Like New. Like New. book. Seller Inventory # ERICA80014757105776
Quantity: 1 available