Transistor Scaling: Volume 913: Methods, Materials and Modeling (MRS Proceedings) - Hardcover

Hardcover

ISBN 10: 1558998691 ISBN 13: 9781558998698

Publisher: Cambridge University Press, 2006

Synopsis

For the past four decades, geometric scaling of silicon CMOS transistors has enabled not only an exponential increase in circuit integration density - Moore's Law - but also a corresponding enhancement in the transistor performance. Simple MOSFET geometric scaling has driven the industry to date. However, as the transistor gate lengths drop below 35nm and the gate oxide thickness is reduced to 1nm, physical limitations such as off-state leakage current and power density make geometric scaling an increasingly challenging task. In order to continue CMOS device scaling, innovations in device structures and materials are required and the industry needs a new scaling vector. Starting at the 90 and 65nm technology generation, strained silicon has emerged as one such innovation. Other device structures such as multigate FETs may be introduced to meet the scaling challenge. This book shares results and physical models related to MOSFETs and to discuss innovative approaches necessary to continue the transistor scaling. Expanded versions of presentations in the areas of technology development are featured

Edition details

• Publisher: Cambridge University Press
• Publication date: 2006
• Language: English
• ISBN 10: 1558998691
• ISBN 13: 9781558998698
• Binding: Hardcover
• Edition number: 1
• Number of pages: 205
• Editor: Thompson Scott, Nouri Faran, Lee Wen-Chin, Tsai Wilman