On-Chip Networks: Second Edition (Synthesis Lectures on Computer Architecture, 40) - Softcover

Jerger, Natalie Enright; Krishna, Tushar; Peh, Li-Shiuan

9781627059145: On-Chip Networks: Second Edition (Synthesis Lectures on Computer Architecture, 40)

Softcover

ISBN 10: 1627059148 ISBN 13: 9781627059145

Publisher: Morgan & Claypool Publishers, 2017

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This book targets engineers and researchers familiar with basic computer architecture concepts who are interested in learning about on-chip networks. This work is designed to be a short synthesis of the most critical concepts in on-chip network design. It is a resource for both understanding on-chip network basics and for providing an overview of state of the-art research in on-chip networks. We believe that an overview that teaches both fundamental concepts and highlights state-of-the-art designs will be of great value to both graduate students and industry engineers. While not an exhaustive text, we hope to illuminate fundamental concepts for the reader as well as identify trends and gaps in on-chip network research.

With the rapid advances in this field, we felt it was timely to update and review the state of the art in this second edition. We introduce two new chapters at the end of the book. We have updated the latest research of the past years throughout the book and also expanded our coverage of fundamental concepts to include several research ideas that have now made their way into products and, in our opinion, should be textbook concepts that all on-chip network practitioners should know. For example, these fundamental concepts include message passing, multicast routing, and bubble flow control schemes.

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About the Author

Natalie Enright Jerger is an Associate Professor and the Percy Edward Hart Professor of Electrical and Computer Engineering in the Edward S. Rogers Sr. Department of Electrical and Computer Engineering at the University of Toronto. She completed her Ph.D. at the University of Wisconsin-Madison in 2008. She received her Master of Science degree from the University of Wisconsin-Madison and Bachelor of Science in Computer Engineering from Purdue University in 2004 and 2002, respectively. Her research interests include multi- and many-core architectures, on-chip networks, cache coherence protocols, memory systems, and approximate computing. Her research is supported by NSERC, Intel, CFI, AMD, and Qualcomm. She was awarded an Alfred P. Sloan Research Fellowship in 2015, Borg Early Career Award in 2015, MICRO Hall of Fame in 2015, the Ontario Professional Engineers Young Engineer Medal in 2014, and the Ontario Ministry of Research and Innovation Early Researcher Award in 2012.

Review

“A comprehensive discourse on the relatively new area of on-chip networks (OCNs) is provided in this book. Research on on-chip networks blends divergent research topics from computer architecture, very-large-scale integration (VLSI), and networks. The target audiences of this book are engineers and researchers familiar with many basic computer architecture concepts who are interested in learning about on-chip networks. The authors are clearly successful in meeting the demand for this broad community of potential readers. They are also motivated to discuss topics ranging from basic concepts in on-chip networks to state-of-the-art design issues. Both of these objectives are nicely met by the authors, and thus the book can be used as a jump-start for newcomers to the OCN area.” – Mohammed Ziaur Rahman for ACM Computing Reviews

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