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Synopsis
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
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About the Author
Krishnendu Chakrabarty is a Professor of Electrical and Computer Engineering at Duke University. He received his PhD from University of Michigan. He is a Fellow of IEEE and a Distinguished Engineer of ACM.
From the Back Cover
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
• Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICs;
• Includes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule optimizations;
• Encompasses all aspects of test as related to 3D ICs, including pre-bond and post-bond test as well as the test optimization and scheduling necessary to ensure that 3D testing remains cost-effective.
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Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs (Hardcover)
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Hardcover. Condition: new. Hardcover. This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9783319023779
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Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable. 264 pp. Englisch. Seller Inventory # 9783319023779
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a comprehensive guide to the challenges and solutions for the testing of TSV-based 3D stacked ICsIncludes in-depth explanation of key test and design-for-test technologies, emerging standards, and test- architecture and test-schedule opti. Seller Inventory # 4496418
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Design-for-test and Test Optimization Techniques for TSV-based 3D Stacked ICs
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Condition: New. Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs Num Pages: 263 pages, 18 black & white illustrations, 115 colour illustrations, 23 black & white tables, biogra. BIC Classification: TJFC; TJFD; UYF. Category: (P) Professional & Vocational. Dimension: 243 x 157 x 16. Weight in Grams: 514. . 2013. 2014th Edition. Hardcover. . . . . Seller Inventory # V9783319023779
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