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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation - Softcover
Synopsis
Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presents design techniques for fast, energy-efficient and timing-predictable memory systems that achieve high performance and low energy consumption. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds.
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About the Author
Prof. Peter Marwedel is well established within the Electronic Design Automation community, he has co-authored four books with us and also published his best-selling Embedded Systems Design (text)book with Springer.
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Fast, Efficient and Predictable Memory Accesses (eng)
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Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation
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Fast, Efficient and Predictable Memory Accesses
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ISBN 13: 9789048172009
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Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Speed improvements in memory systems have not kept pace with the speed improvements of processors, leading to embedded systems whose performance is limited by the memory. This book presents design techniques for fast, energy-efficient and timing-predictable memory systems that achieve high performance and low energy consumption. In addition, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds. 272 pp. Englisch. Seller Inventory # 9789048172009
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Fast, Efficient and Predictable Memory Accesses
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Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Focus on the increasing importance of memory system design in embedded systemsSolutions to the problems of energy-inefficient and slow memory systems with unpredictable access timesDemonstration of the benefits of exploiting architectural f. Seller Inventory # 5821044
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Fast, Efficient and Predictable Memory Accesses : Optimization Algorithms for Memory Architecture Aware Compilation
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Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy. Seller Inventory # 9789048172009
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Fast, Efficient and Predictable Memory Accesses: Optimization Algorithms for Memory Architecture Aware Compilation
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Fast, Efficient and Predictable Memory Accesses
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ISBN 10: 9048172004
ISBN 13: 9789048172009
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Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Fast, Efficient and Predictable Memory Accesses presents techniques for designing fast, energy-efficient and timing predictable memory systems. By using a careful combination of compiler optimizations and architectural improvements, we can achieve more than what would be feasible at one of the levels in isolation. The described optimization algorithms achieve the goals of high performance and low energy consumption. In addition to these benefits, the use of scratchpad memories significantly improves the timing predictability of the entire system, leading to tighter worst case execution time bounds (WCET). The WCET is a relevant design parameter for all timing critical systems. In addition, the book covers algorithms to exploit the power down modes of main memories in SDRAM technology, as well as the execute-in-place feature of Flash memories. The final chapter considers the impact of the register file, which is also part of the memory hierarchy.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 272 pp. Englisch. Seller Inventory # 9789048172009
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