Items related to Towards a Design Flow for Reversible Logic
Synopsis
1. Introduction. 2. Preliminaries. 2.1. Background. 2.2. Decision Diagrams. 2.3. Satisfiability Solvers. 3. Synthesis of Reversible Logic. 3.1. Current Synthesis Steps . 3.2. BDD-based Synthesis. 3.3. SyReC: A Reversible Hardware Language. 3.4. Summary and Future Work. 4. Exact Synthesis of Reversible Logic. 4.1. Main Flow. 4.2. SAT-based Exact Synthesis. 4.3. Improved Exact Synthesis. 4.4. Summary and Future Work. 5. Embedding of Irreversible Functions. 5.1. Embedding Problem. 5.2. Don't Care Assignment. 5.3. Synthesis with Output Permutation. 5.4. Summary and Future Work. 6. Optimization. 6.1. Adding Lines to Reduce Circuit Cost. 6.2. Reducing the Number of Circuit Lines. 6.3. Optimizing Circuits for Linear Nearest Neighbor Architectures. 6.4. Summary and Future Work. 7. Formal Veri?cation and Debugging. 7.1. Equivalence Checking. 7.2. Automated Debugging and Fixing. 7.3. Summary and Future Work. 8. Summary and Conclusions. References. Index.
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Review
From the reviews:
“This is a book about the present and the future of computing machines. ... At the end of the book a list of 144 refs are included giving the reader the possibility to know more than there are in the book. ... the book represents an excellent text at a post-graduate level aiming to give to the researchers the basic ideas and techniques in this new emerging domain.” (Dumitru Stanomir, Zentralblatt MATH, Vol. 1210, 2011)"About this title" may belong to another edition of this title.
- PublisherSpringer
- Publication date2010
- ISBN 10 9048195802
- ISBN 13 9789048195800
- BindingPaperback
- LanguageEnglish
- Number of pages200
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