Analysis and Design of Networks-on-Chip Under High Process Variation

Rabab Ezz-Eldin

ISBN 10: 3319798375 / ISBN 13: 9783319798370

Published by Springer International Publishing, Springer International Publishing Mär 2019, 2019

About this Item

Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 164 pp. Englisch.

Seller Inventory # 9783319798370

Bibliographic Details

• Title: Analysis and Design of Networks-on-Chip Under High Process Variation
• Publisher: Springer International Publishing, Springer International Publishing Mär 2019
• Publication Date: 2019
• Language: English
• ISBN 10: 3319798375
• ISBN 13: 9783319798370
• Binding: Taschenbuch
• Condition: Neu
• Dimensions: 235W x 155H x 10D millimeters 235 millimeters width by 155 millimeters height by 10 millimeters depth
• Weight: 260 grams

About this title

Synopsis

This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.

About the Author

Magdy Ali El-Moursy is an Associate Professor in the Microelectronics Department of the Electronics Research Institute, Cairo, Egypt and Staff Engineer at Design Creation and Synthesis Division of Mentor Graphics Corporation, Cairo, Egypt.