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Rabab Ezz Eldin (26 results)
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Hardcover. Condition: As New. 1. Auflage. Unread, like new. Immediately dispatched from Germany.
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High-Performance and Low-Power Network on Chip Switch
Language: English
Published by LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3848401452 ISBN 13: 9783848401451
Condition: New.
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High-Performance and Low-Power Network on Chip Switch | Network on Chip
Language: English
Published by LAP Lambert Academic Publishing, 2012
ISBN 10: 3848401452 ISBN 13: 9783848401451
Taschenbuch. Condition: Neu. High-Performance and Low-Power Network on Chip Switch | Network on Chip | Rabab Ezz-Eldin (u. a.) | Taschenbuch | Englisch | LAP Lambert Academic Publishing | EAN 9783848401451 | Verantwortliche Person für die EU: preigu GmbH & Co. KG, Lengericher Landstr. 19, 49078 Osnabrück, mail[at]preigu[dot]de | Anbieter: preigu.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
US$ 134.62
US$ 16.29 shipping
Ships from United Kingdom to U.S.A.Quantity: Over 20 available
Add to basketCondition: New. In.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
US$ 134.62
US$ 16.29 shipping
Ships from United Kingdom to U.S.A.Quantity: Over 20 available
Add to basketCondition: New. In.
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High-Performance and Low-Power Network on Chip Switch: Network on Chip
Language: English
Published by LAP LAMBERT Academic Publishing, 2012
ISBN 10: 3848401452 ISBN 13: 9783848401451
US$ 134.42
US$ 33.98 shipping
Ships from United Kingdom to U.S.A.Quantity: 1 available
Add to basketPaperback. Condition: Like New. LIKE NEW. SHIPS FROM MULTIPLE LOCATIONS. book.
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Condition: New. pp. 141.
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Condition: New. pp. 300.
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US$ 174.17
US$ 13.59 shipping
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Add to basketPaperback. Condition: Brand New. reprint edition. 164 pages. 9.25x6.10x0.37 inches. In Stock.
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US$ 176.39
US$ 13.59 shipping
Ships from United Kingdom to U.S.A.Quantity: 2 available
Add to basketHardcover. Condition: Brand New. 9.25x6.25x0.50 inches. In Stock.
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Taschenbuch. Condition: Neu. Analysis and Design of Networks-on-Chip Under High Process Variation | Rabab Ezz-Eldin (u. a.) | Taschenbuch | xxi | Englisch | 2019 | Springer | EAN 9783319798370 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing, Springer International Publishing, 2019
ISBN 10: 3319798375 ISBN 13: 9783319798370
Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing, 2015
ISBN 10: 3319257641 ISBN 13: 9783319257648
Buch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.
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Condition: new. Questo è un articolo print on demand.
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Condition: new. Questo è un articolo print on demand.
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High-Performance and Low-Power Network on Chip Switch : Network on Chip
Language: English
Published by LAP Lambert Academic Publishing, 2012
ISBN 10: 3848401452 ISBN 13: 9783848401451
Taschenbuch. Condition: Neu. nach der Bestellung gedruckt Neuware - Printed after ordering - Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). Two power reduction techniques are exploited to design the proposed switch. The proposed NoC switch employs power supply gating to reduce the power dissipation. Adaptive virtual channel (AVC) is proposed as a novel technique to reduce power dissipation of the NoC switch. AVC technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing tree. Moreover, power gating reduces the average leakage power consumption of proposed switch. The proposed techniques reduce the leakage and dynamic power dissipation of the switch.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing Dez 2015, 2015
ISBN 10: 3319257641 ISBN 13: 9783319257648
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. 164 pp. Englisch.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing Mrz 2019, 2019
ISBN 10: 3319798375 ISBN 13: 9783319798370
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns. 164 pp. Englisch.
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US$ 155.63
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Ships from United Kingdom to U.S.A.Quantity: 4 available
Add to basketCondition: New. Print on Demand pp. 141.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing, 2015
ISBN 10: 3319257641 ISBN 13: 9783319257648
US$ 111.84
US$ 57.65 shipping
Ships from Germany to U.S.A.Quantity: Over 20 available
Add to basketGebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Demonstrates the impact of process variation on Networks-on-Chipof different topologiesIncludes an overview of the synchronous clocking scheme, clockdistribution network, main building blocks in asynchronous NoC design,handshake protocols, data en.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer International Publishing, 2019
ISBN 10: 3319798375 ISBN 13: 9783319798370
US$ 111.84
US$ 57.65 shipping
Ships from Germany to U.S.A.Quantity: Over 20 available
Add to basketCondition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Demonstrates the impact of process variation on Networks-on-Chipof different topologiesIncludes an overview of the synchronous clocking scheme, clockdistribution network, main building blocks in asynchronous NoC design,handshake protocols, data en.
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US$ 165.07
US$ 8.84 shipping
Ships from United Kingdom to U.S.A.Quantity: 4 available
Add to basketCondition: New. Print on Demand pp. 300.
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Condition: New. PRINT ON DEMAND pp. 300.
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Condition: New. PRINT ON DEMAND pp. 141.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer, Springer Mär 2019, 2019
ISBN 10: 3319798375 ISBN 13: 9783319798370
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 164 pp. Englisch.
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Analysis and Design of Networks-on-Chip Under High Process Variation
Language: English
Published by Springer, Springer Dez 2015, 2015
ISBN 10: 3319257641 ISBN 13: 9783319257648
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Buch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -This book describes in detail the impact of process variations on Network-on-Chip (NoC) performance. The authors evaluate various NoC topologies under high process variation and explain the design of efficient NoCs, with advanced technologies. The discussion includes variation in logic and interconnect, in order to evaluate the delay and throughput variation with different NoC topologies. The authors describe an asynchronous router, as a robust design to mitigate the impact of process variation in NoCs and the performance of different routing algorithms is determined with/without process variation for various traffic patterns. Additionally, a novel Process variation Delay and Congestion aware Routing algorithm (PDCR) is described for asynchronous NoC design, which outperforms different adaptive routing algorithms in the average delay and saturation throughput for various traffic patterns.Springer-Verlag KG, Sachsenplatz 4-6, 1201 Wien 164 pp. Englisch.
