Constraining Designs for Synthesis and Timing Analysis

Gangadharan, Sridhar; Churiwala, Sanjay

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ISBN 10: 1461432685 ISBN 13: 9781461432685
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This guide to timing constraints in integrated circuit design shows how to maximize performance of IC designs by specifying timing requirements correctly. Coverage includes such design aspects as synthesis, static timing analysis and placement and routing. Num Pages: 226 pages, biography. BIC Classification: TJFC; UYF. Category: (P) Professional & Vocational. Dimension: 243 x 158 x 20. Weight in Grams: 522. . 2013. Hardback. . . . . Books ship from the US and Ireland. Seller Inventory # V9781461432685

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Synopsis:

This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints.

About the Author:

Sanjay Churiwala is an Electronics Engineer from IIT Kharagpur, with two decades of experience in EDA and VLSI. His interest areas include rule checking, synthesis, simulation, STA, Power and Clock Domain Crossings and Synchronization. He currently works at Hyderabad office of Xilinx.

Sridhar Gangadharan  is a Senior Product Engineering Director for Timing Constraints Analysis and SpyGlass  RTL Analysis Products at Atrenta. He has over 20 years of experience in the electronic design automation industry. His interest areas include RTL verification, timing closure, delay calculation and memory compilers. He holds a Bachelors degree in Computer Science and Engineering from Indian Institute of Technology in Delhi. He is based in San Jose, CA.

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Bibliographic Details

Title: Constraining Designs for Synthesis and ...
Publisher: Springer-Verlag New York Inc.
Publication Date: 2013
Binding: Hardcover
Condition: New

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Condition: Sehr gut. Zustand: Sehr gut | Seiten: 256 | Sprache: Englisch | Produktart: Bücher | This book serves as a hands-on guide to timing constraints in integrated circuit design.  Readers will learn to maximize performance of their IC designs, by specifying timing requirements correctly.  Coverage includes key aspects of the design flow impacted by timing constraints, including synthesis, static timing analysis and placement and routing.  Concepts needed for specifying timing requirements are explained in detail and then applied to specific stages in the design flow, all within the context of Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints. Seller Inventory # 23271956/2

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Gebunden. Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Provides a hands-on guide to create constraints for synthesis and timing analysis, using Synopsys Design Constraints (SDC), the industry-leading format for specifying constraints Explains fundamental concepts around SDC constraints and its applica. Seller Inventory # 4198073

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Buch. Condition: Neu. Constraining Designs for Synthesis and Timing Analysis | A Practical Guide to Synopsys Design Constraints (SDC) | Sanjay Churiwala (u. a.) | Buch | xxvii | Englisch | 2013 | Springer US | EAN 9781461432685 | Verantwortliche Person für die EU: Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg, juergen[dot]hartmann[at]springer[dot]com | Anbieter: preigu Print on Demand. Seller Inventory # 106127290

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