Digital Timing Macromodeling for VLSI Design Verification
Kong, Jeong-Taek, Overhauser, David V.
ISBN 10: 1461359821 ISBN 13: 9781461359821
Published by Springer, 2012
New
Soft cover
From
Kennys Bookstore, Olney, MD, U.S.A.
Seller rating 5 out of 5 stars
AbeBooks Seller since October 9, 2009
This specific item is no longer available.
About this Item
Description:
2012. Paperback. . . . . . Books ship from the US and Ireland. Seller Inventory # V9781461359821
Synopsis:
Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.
The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.
"About this title" may belong to another edition of this title.
Bibliographic Details
Title: Digital Timing Macromodeling for VLSI Design...
Publisher: Springer
Publication Date: 2012
Binding: Soft cover
Condition: New
Top Search Results from the AbeBooks Marketplace
Seller Image
Digital Timing Macromodeling for VLSI Design Verification
Print on DemandSeller: moluna, Greven, Germany
Seller rating 4 out of 5 stars
Condition: New. Dieser Artikel ist ein Print on Demand Artikel und wird nach Ihrer Bestellung fuer Sie gedruckt. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timi. Seller Inventory # 4194192
Quantity: Over 20 available
Seller Image
Digital Timing Macromodeling for Vlsi Design Verification
Seller: GreatBookPrices, Columbia, MD, U.S.A.
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # 19850084-n
Quantity: 15 available
Stock Image
Digital Timing Macromodeling for VLSI Design Verification (Paperback)
Published by
Springer-Verlag New York Inc., New York, NY, 2012
ISBN 10: 1461359821
ISBN 13: 9781461359821
New
Paperback
Seller: Grand Eagle Retail, Bensenville, IL, U.S.A.
Seller rating 5 out of 5 stars
Paperback. Condition: new. Paperback. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. Shipping may be from multiple locations in the US or from the UK, depending on stock availability. Seller Inventory # 9781461359821
Quantity: 1 available
Stock Image
Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)
Seller: Lucky's Textbooks, Dallas, TX, U.S.A.
Seller rating 5 out of 5 stars
Condition: New. Seller Inventory # ABLIING23Mar2716030032658
Quantity: Over 20 available
Stock Image
Digital Timing Macromodeling for VLSI Design Verification (The Springer International Series in Engineering and Computer Science)
Seller: Ria Christie Collections, Uxbridge, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. In. Seller Inventory # ria9781461359821_new
Quantity: Over 20 available
Seller Image
Digital Timing Macromodeling for VLSI Design Verification
Published by
Springer US, Springer US Okt 2012, 2012
ISBN 10: 1461359821
ISBN 13: 9781461359821
New
Taschenbuch
Seller: BuchWeltWeit Ludwig Meier e.K., Bergisch Gladbach, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - it takes 3-4 days longer - Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. 292 pp. Englisch. Seller Inventory # 9781461359821
Quantity: 2 available
Seller Image
Digital Timing Macromodeling for VLSI Design Verification
Published by
Springer US, Springer New York Okt 2012, 2012
ISBN 10: 1461359821
ISBN 13: 9781461359821
New
Taschenbuch
Seller: buchversandmimpf2000, Emtmannsberg, BAYE, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. This item is printed on demand - Print on Demand Titel. Neuware -Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels.The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques.Springer Verlag GmbH, Tiergartenstr. 17, 69121 Heidelberg 292 pp. Englisch. Seller Inventory # 9781461359821
Quantity: 1 available
Seller Image
Digital Timing Macromodeling for VLSI Design Verification
Published by
Springer US, Springer New York, 2012
ISBN 10: 1461359821
ISBN 13: 9781461359821
New
Taschenbuch
Seller: AHA-BUCH GmbH, Einbeck, Germany
Seller rating 5 out of 5 stars
Taschenbuch. Condition: Neu. Druck auf Anfrage Neuware - Printed after ordering - Digital Timing Macromodeling for VLSI Design Verification first of all provides an extensive history of the development of simulation techniques. It presents detailed discussion of the various techniques implemented in circuit, timing, fast-timing, switch-level timing, switch-level, and gate-level simulation. It also discusses mixed-mode simulation and interconnection analysis methods. The review in Chapter 2 gives an understanding of the advantages and disadvantages of the many techniques applied in modern digital macromodels. The book also presents a wide variety of techniques for performing nonlinear macromodeling of digital MOS subcircuits which address a large number of shortcomings in existing digital MOS macromodels. Specifically, the techniques address the device model detail, transistor coupling capacitance, effective channel length modulation, series transistor reduction, effective transconductance, input terminal dependence, gate parasitic capacitance, the body effect, the impact of parasitic RC-interconnects, and the effect of transmission gates. The techniques address major sources of errors in existing macromodeling techniques, which must be addressed if macromodeling is to be accepted in commercial CAD tools by chip designers. The techniques presented in Chapters 4-6 can be implemented in other macromodels, and are demonstrated using the macromodel presented in Chapter 3. The new techniques are validated over an extremely wide range of operating conditions: much wider than has been presented for previous macromodels, thus demonstrating the wide range of applicability of these techniques. Seller Inventory # 9781461359821
Quantity: 1 available
Stock Image
Digital Timing Macromodeling for VLSI Design Verification
Seller: Books Puddle, New York, NY, U.S.A.
Seller rating 4 out of 5 stars
Condition: New. pp. 294 Index. Seller Inventory # 2697846705
Quantity: 4 available
Stock Image
Digital Timing Macromodeling for VLSI Design Verification
Print on DemandSeller: Majestic Books, Hounslow, United Kingdom
Seller rating 5 out of 5 stars
Condition: New. Print on Demand pp. 294 Figures, 49:B&W 6.14 x 9.21 in or 234 x 156 mm (Royal 8vo) Perfect Bound on White w/Gloss Lam. Seller Inventory # 94550638
Quantity: 4 available