Effect of Underlap On Device Performance of GaN Based DG-MOSFET

Md. Rokib Hasan

ISBN 10: 3659920134 / ISBN 13: 9783659920134

Published by LAP LAMBERT Academic Publishing Jul 2016, 2016

About this Item

This item is printed on demand - Print on Demand Titel. Neuware -GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.VDM Verlag, Dudweiler Landstraße 99, 66123 Saarbrücken 68 pp. Englisch.

Seller Inventory # 9783659920134

Bibliographic Details

• Title: Effect of Underlap On Device Performance of GaN Based DG-MOSFET
• Publisher: LAP LAMBERT Academic Publishing Jul 2016
• Publication Date: 2016
• Language: English
• ISBN 10: 3659920134
• ISBN 13: 9783659920134
• Binding: Taschenbuch
• Condition: Neu
• Dust Jacket Condition: Dust Jacket Included
• Dimensions: 220W x 150H x 5D millimeters 220 millimeters width by 150 millimeters height by 5 millimeters depth
• Weight: 119 grams

About this title

Synopsis

GaN based double gate (DG) metal oxide semiconductor field effect transistors (MOSFETs) with a gate length of 10 nm have been designed for the next generation logic applications. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are 66.5 mV/decade and 30 mV/V, respectively. The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate.The length of gate underlap is varied from 1 to 4 nm. The underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN based DG MOSFETs shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

About the Author

I am Md. Rokib Hasan. My home town is Mymensingh, Bangladesh. I have completed my B.Sc. in Electrical and Electronics Engineering from American International University- Bangladesh (AIUB).I was nominated as a General Secretary of "IEEE AIUB STUDENT BRANCH" for 2015.I am an active member of IEEE for three years(2014-2016).